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PI7C7300D 3-port pci-to-pci bridge revision 1.01 3545 north 1 st street, san jose, ca 95134 telephone: 1-877-pericom (1-877-737-4266) fax: 408-435-1100 internet: http://www.pericom.com
PI7C7300D 3-port pci-to-pci bridge page 2 of 107 pericom semiconductor november 2005 - revision 1.01 life support policy pericom semiconductor corporation? s products are not authorized for use as criti cal components in life support devices or syste ms unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of psc. 1. life support devices or systems are devices or systems which: a) are intended for surgical implant into the body or b) support or sustain life and whose fa ilure to perform, when properly used in accordance with in structions for use provided in the labeling, can be reasonably expected to result in a significan t injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to aff ect its safety or effectiveness. pericom semiconductor corpora tion reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possi ble product. pericom semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a pe ricom semiconductor product. the company makes no representations that circuitry described herein is free from patent infringement or ot her rights of third parties which may result from its use . no license is granted by implication or otherwise under any patent, patent rights or other right s, of pericom semiconductor corporation. all other trademarks are of their respective companies.
PI7C7300D 3-port pci-to-pci bridge page 3 of 107 pericom semiconductor november 2005 - revision 1.01 revision history revision date description 1.00 09/21/2004 initial release of datasheet 1.01 11/21/2005 removed ?advance in formation? from datasheet renamed pin y4 from bypass to by_pass
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PI7C7300D 3-port pci-to-pci bridge page 5 of 107 pericom semiconductor november 2005 - revision 1.01 table of contents 1 introduction ............................................................................................................................ 11 2 block diagram ......................................................................................................................... 12 3 signal definitions ................................................................................................................. 13 3.1 signal types ........................................................................................................................ 13 3.2 primary bus interface signals ................................................................................ 13 3.3 secondary bus interface signals .......................................................................... 15 3.4 clock signals ..................................................................................................................... 17 3.5 miscellaneous signals ................................................................................................. 17 3.6 compact pci hot-swap signals .................................................................................. 17 3.7 jtag boundary scan signals ..................................................................................... 18 3.8 power and ground .......................................................................................................... 18 3.9 PI7C7300D pbga pin list .................................................................................................... 18 4 pci bus operation ................................................................................................................... 21 4.1 types of transactions .................................................................................................. 21 4.2 single address phase ..................................................................................................... 22 4.3 dual address phase ........................................................................................................ 22 4.4 device select (devsel#) generation ...................................................................... 23 4.5 data phase ........................................................................................................................... 23 4.6 write transactions ........................................................................................................ 23 4.6.1 memory write transactions .................................................................................. 24 4.6.2 memory write and invalidate transactions .................................................. 25 4.6.3 delayed write transactions ................................................................................. 25 4.6.4 write transaction address boundaries .......................................................... 26 4.6.5 buffering multiple write transactions ......................................................... 26 4.6.6 fast back-to-back write transactions ............................................................ 27 4.7 read transactions .......................................................................................................... 27 4.7.1 prefetchable read transactions ....................................................................... 27 4.7.2 non-prefetchable read transactions ............................................................. 27 4.7.3 read prefetch address boundaries .................................................................. 28 4.7.4 delayed read requests ........................................................................................... 30 4.7.5 delayed read completion with target ........................................................... 30 4.7.6 delayed read completion on initiator bus ................................................... 32 4.7.7 fast back-to-back read transaction ................................................................ 32 4.8 configuration transactions .................................................................................... 33 4.8.1 type 0 access to PI7C7300D ...................................................................................... 33 4.8.2 type 1 to type 0 conversion ................................................................................... 34 4.8.3 type 1 to type 1 forwarding .................................................................................. 35 4.8.4 special cycles ............................................................................................................. 36 4.9 transaction termination ........................................................................................... 37 4.9.1 master termination initiated by PI7C7300D ..................................................... 37 4.9.2 master abort received by PI7C7300D .................................................................. 38 4.9.3 target termination received by PI7C7300D ..................................................... 38 4.9.4 target termination initiated by PI7C7300D ..................................................... 41 4.10 concurrent mode operation ..................................................................................... 42 5 address decoding .................................................................................................................. 42
PI7C7300D 3-port pci-to-pci bridge page 6 of 107 pericom semiconductor november 2005 - revision 1.01 5.1 address ranges ................................................................................................................. 43 5.2 i/o address decoding ...................................................................................................... 43 5.2.1 i/o base and limit address register ................................................................... 44 5.2.2 isa mode.......................................................................................................................... 45 5.3 memory address decoding ......................................................................................... 45 5.3.1 memory-mapped i/o base and limit address registers .............................. 46 5.3.2 prefetchable memory base and limit address registers ....................... 47 5.4 vga support ......................................................................................................................... 48 5.4.1 vga mode ........................................................................................................................ 48 5.4.2 vga snoop mode .......................................................................................................... 48 6 transaction ordering ........................................................................................................ 49 6.1 transactions governed by ordering rules ..................................................... 49 6.2 general ordering guidelines ................................................................................... 50 6.3 ordering rules .................................................................................................................. 50 6.4 data synchronization.................................................................................................. 52 7 error handling ....................................................................................................................... 52 7.1 address parity errors .................................................................................................. 52 7.2 data parity errors ......................................................................................................... 53 7.2.1 configuration write transactio ns to configuration space ............... 53 7.2.2 read transactions ..................................................................................................... 53 7.2.3 delayed write transactions ................................................................................. 54 7.2.4 posted write transactions .................................................................................... 56 7.3 data parity error reporting summary .............................................................. 58 7.4 system error (serr#) reporting ............................................................................... 63 8 exclusive access .................................................................................................................... 63 8.1 concurrent locks ........................................................................................................... 64 8.2 acquiring exclusive access across PI7C7300D .................................................. 64 8.2.1 locked transactions in dowstream direction ............................................ 64 8.2.2 locked transaction in upstream direction .................................................. 65 8.3 ending exclusive access ............................................................................................. 65 9 pci bus arbitration ............................................................................................................... 66 9.1 primary pci bus arbitration ...................................................................................... 67 9.2 secondary pci bus arbitration ................................................................................ 67 9.2.1 secondary busarbitration using the internal arbiter ........................... 67 9.2.2 preemption ................................................................................................................... 69 9.2.3 secondary bus arbitration using an external arbiter ............................ 69 9.2.4 bus parking ................................................................................................................... 69 10 compact pci hot swap ..................................................................................................... 70 11 clocks ............................................................................................................................... ........ 70 11.1 primary clock inputs .................................................................................................... 70 11.2 secondary clock outputs .......................................................................................... 70 12 reset ............................................................................................................................... ............ 71 12.1 primary interface reset .............................................................................................. 71 12.2 secondary interface reset ........................................................................................ 71
PI7C7300D 3-port pci-to-pci bridge page 7 of 107 pericom semiconductor november 2005 - revision 1.01 13 supported commands ...................................................................................................... 72 13.1 primary interface ........................................................................................................... 72 13.2 secondary interface ..................................................................................................... 73 14 configuration registers ............................................................................................. 73 14.1 configuration register 1 and 2 ................................................................................ 75 14.1.1 vendor id register ? offset 00h ........................................................................... 75 14.1.2 device id register ? offset 00h ............................................................................ 76 14.1.3 command register ? offset 04h ........................................................................... 76 14.1.4 status register ? offset 04h.................................................................................. 77 14.1.5 revision id register ? offset 08h ......................................................................... 78 14.1.6 class code register ? offest 08h ........................................................................ 78 14.1.7 cache line size register ? offset 0ch ............................................................... 78 14.1.8 primary latency timer register ? offset 0ch ................................................ 78 14.1.9 header type register ? offset 0ch ..................................................................... 79 14.1.10 primary bus number register ? offset 18h ................................................. 79 14.1.11 secondary (s1 or s2) bus number register ? offset 18h .......................... 79 14.1.12 subordinate (s1 or s2) bus number register ? offset 18h ...................... 79 14.1.13 secondary latency timer register ? offset 18h ...................................... 79 14.1.14 i/o base register ? offset 1ch ........................................................................... 80 14.1.15 i/o limit register ? offset 1ch .......................................................................... 80 14.1.16 secondary status register ? offset 1ch ...................................................... 80 14.1.17 memory base register ? offset 20h ................................................................. 81 14.1.18 memory limit register ? offset 20h ................................................................ 81 14.1.19 prefetchable memory base register ? offset 24h .................................. 82 14.1.20 prefetchable memory limit register ? offset 24h ................................. 82 14.1.21 prefetchable memory base address u pper 32-bits register ? offset 28h .............................................................................................................................. .......... 82 14.1.22 prefetchable memory limit address upper 32-bits register ? offset 2ch .............................................................................................................................. .......... 82 14.1.23 i/o base address upper 16-bits register ? offset 30h ................................... 83 14.1.24 i/o limit address upper 16-bits register ? offset 30h ............................. 83 14.1.25 ecp pointer register ? offset 34h ................................................................... 83 14.1.26 bridge control register ? offset 3ch .......................................................... 83 14.1.27 diagnostic / chip control register ? offset 40h ..................................... 85 14.1.28 arbiter control register ? offset 40h ......................................................... 86 14.1.29 upstream memory control register ? offset 48h ................................... 86 14.1.30 hot swap switch time slot register ? offset 4ch .................................... 86 14.1.31 upstream (s1 or s2 to p) memory base register ? offset 50h ................... 87 14.1.32 upstream (s1 or s2 to p) memory limit register ? offset 50h .................. 87 14.1.33 upstream (s1 or s2 to p) memory base upper 32-bits register ? offset 54h .............................................................................................................................. .......... 87 14.1.34 upstream (s1 or s2 to p) memory limit upper 32 bits register ? offset 58h .............................................................................................................................. .......... 88 14.1.35 p_serr# event disable register ? offset 64h .............................................. 88 14.1.36 secondary clock control register ? offset 68h .................................... 89 14.1.37 port option register ? offset 74h .................................................................. 89 14.1.38 master timeout counter register ? offset 74h ....................................... 91 14.1.39 retry counter register ? offset 78h ............................................................. 91 14.1.40 sampling timer register ? offset 7ch ........................................................... 91 14.1.41 secondary successful i/o read counter register ? offset 80h ....... 91
PI7C7300D 3-port pci-to-pci bridge page 8 of 107 pericom semiconductor november 2005 - revision 1.01 14.1.42 secondary successful i/o write counter register ? offset 84h ...... 91 14.1.43 secondary successful memory read counter register ? offset 88h 92 14.1.44 secondary successful memory write counter register ? offset 8ch .............................................................................................................................. .......... 92 14.1.45 primary successful i/o read counter register ? offset 90h ............. 92 14.1.46 primary successful i/o write counter register ? offset 94h ............ 92 14.1.47 primary successful memory read counter register ? offset 98h .. 92 14.1.48 primary successful memory write counter register ? offset 9ch 93 14.1.49 capability id register ? offset b0h ................................................................ 93 14.1.50 next pointer register ? offset b0h ................................................................ 93 14.1.51 slot number register ? offset b0h ................................................................. 93 14.1.52 chassis number register ? offset b0h ........................................................... 93 14.1.53 capability id register ? offset c0h ................................................................ 94 14.1.54 next pointer register ? offset c0h ................................................................ 94 14.1.55 hot swap control and status register ? offset c0h ............................. 94 15 bridge behavior .................................................................................................................. 94 15.1 bridge actions for various cycle types ............................................................ 95 15.2 transaction ordering .................................................................................................. 95 15.3 abnormal termination (initiated by bridge master) ................................. 96 15.3.1 master abort ................................................................................................................ 96 15.3.2 parity and error reporting .................................................................................. 96 15.3.3 reporting parity errors ......................................................................................... 96 15.3.4 secondary idsel mapping ....................................................................................... 97 16 ieee 1149.1 compatible jtag controller ............................................................. 97 16.1 boundary scan architecture .................................................................................. 97 16.1.1 tap pins ............................................................................................................................ 98 16.1.2 instruction register ................................................................................................ 98 16.2 boundary-scan instruction set .............................................................................. 99 16.3 tap test data registers ................................................................................................ 99 16.4 bypass register ............................................................................................................... 100 16.5 boundary-scan register ........................................................................................... 100 16.6 tap controller ............................................................................................................... 100 17 electrical and timing specifications ............................................................... 103 17.1 maximum ratings ........................................................................................................... 103 17.2 3.3v dc specifications ................................................................................................... 104 17.3 3.3v ac specifications ................................................................................................... 105 17.4 primary and secondary buses at 66mh z clock timing .............................. 106 17.5 primary and secondary buses at 33mh z clock timing .............................. 106 17.6 power consumption ...................................................................................................... 106 18 272-pin pbga package figure ...................................................................................... 107 18.1 part number ordering information ................................................................... 107
PI7C7300D 3-port pci-to-pci bridge page 9 of 107 pericom semiconductor november 2005 - revision 1.01 list of tables t able 4-1 pci transactions ........................................................................................................... 21 t able 4-2 write transaction forwarding ........................................................................... 23 t able 4-3 write transaction di sconnect address boundaries ............................... 26 t able 4-4 read prefetc h address boundaries ................................................................... 29 t able 4-5 read transaction prefetching ............................................................................. 30 t able 4-6 device number to idsel s1_ad or s2_ad pin mapping ................................... 34 t able 4-7 delayed write target termination response .............................................. 39 t able 4-8 response to posted write target termination ............................................ 39 t able 4-9 response to delayed read target termination .......................................... 40 t able 6-1 summary of transaction ordering .................................................................... 50 t able 7-1 setting the primary interface detected parity error bit ................... 58 t able 7-2 setting secondary interface detected parity error bit ...................... 58 t able 7-3 setting primary interface data parity error detected bit ................ 59 t able 7-4 setting secondary interface data parity error detected bit .......... 59 t able 7-5 assertion of p_perr# .................................................................................................... 60 t able 7-6 assertion of s_perr# .................................................................................................... 62 t able 7-7 assertion of p_serr# for data parity errors ............................................... 62 t able 16-1 tap pins .............................................................................................................................. 9 9 t able 16-2 jtag boundary register order ......................................................................... 101 list of figures f igure 9-1 secondary arbiter example .................................................................................. 68 f igure 16-1 test access port block diagram ....................................................................... 98 f igure 17-1 pci signal timing measurement conditions .............................................. 105 f igure 18-1 272-pin pbga package ............................................................................................... 107
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PI7C7300D 3-port pci-to-pci bridge 1 introduction product description the PI7C7300D is pericom semiconductor?s s econd-generation pci-pci bridge and is an updated revision to the pi7c7300a. it is designed to be fully compliant with the 32- bit, 66mhz implementation of the pci local bus specification, revision 2.2. the PI7C7300D supports only synchronous bus transactions between devices on the primary bus running at 33mhz to 66mhz and the sec ondary buses operating at either 33mhz or 66mhz. the primary and secondary buses can also operate in concurrent mode, resulting in added increase in system perform ance. concurrent bus operation off-loads and isolates unnecessary traffic from the prim ary bus; thereby enab ling a master and a target device on the same secondary pci bus to communicate even while the primary bus is busy. in addition, the secondary buses have load balancing capability, allowing faster devices to be isolated away from slower devices. among the other features supported by the PI7C7300D are: support for up to 15 devices on the secondary buses, compact pci hot swap (picmg 2.1, r1.0) friendly support and dual addressing cycle. product features ? 32-bit primary and two secondary ports run up to 66mhz ? all 3 ports compliant with the pci local bus specification, revision 2.2 ? compliant with pci-to-pci bridge architecture specification, revision 1.1 . - all i/o and memory commands - type 1 to type 0 configuration conversion - type 1 to type 1 configuration forwarding - type 1 configuration write to special cycle conversion ? concurrent primary to secondary bus ope ration and independent intra-secondary port channel to reduce tr affic on the primary port ? provides internal arbitration for one set of eight secondary bus masters (s1 bus) and one set of seven (eight if hot swap is disabled) secondary bus masters (s2 bus) - programmable 2-level priority arbiter - disable control for use of external arbiter ? supports posted write buffers in all directions ? three 128 byte fifo?s for delay transactions ? three 128 byte fifo?s for posted memory transactions ? enhanced address decoding - 32-bit i/o address range - 32-bit memory-mapped i/o address range - vga addressing and vga palette snooping - isa-aware mode for legacy support in the first 64kb of i/o address range ? dual addressing cycle (64-bit) ? supports system transaction ordering rules ? tri-state control of output buffers on secondary buses ? compact pci hot swap (picmg 2.1, r1.0) friendly support ? industrial temperature range ?40c to 85c ? ieee 1149.1 jtag interface support ? 3.3v core; 3.3v pci i/o inte rface with 5v i/o tolerance ? 272-pin plastic bga package page 11 of 107 pericom semiconductor november 2005 - revision 1.01
PI7C7300D 3-port pci-to-pci bridge PI7C7300D 3-port pci-to-pci bridge 2 block diagram 2 block diagram page 12 of 107 pericom semiconductor november 2005 - revision 1.01 page 12 of 107 pericom semiconductor november 2005 - revision 1.01
PI7C7300D 3-port pci-to-pci bridge page 13 of 107 pericom semiconductor november 2005 - revision 1.01 3 signal definitions 3.1 signal types signal type description pi pci input (3.3v, 5v tolerant) piu pci input (3.3v, 5v tolerant) with weak pull-up pid pci input (3.3v, 5v tolerant) with weak pull-down po pci output (3.3v) pb pci tri-state bidirectional (3.3v, 5v tolerant) psts pci sustained tri-state bi-directional (active low signal which must be driven inactive for one cycle before being tri- stated to ensure high performance on a shared signal line) pts pci tri-state output pod pci output which either drives low (active state) or tri-state 3.2 primary bus interface signals name pin # type description p_ad[31:0] y7, w7, y8, w8, v8, u8, y9, w9, w10, v10, y11, v11, u11, y12, w12, v12, v16, w16, y16, w17, y17, u18, w18, y18, u19, w19, y19, u20, v20, y20, t17, r17 pb primary address/data. multiplexed address and data bus. address is indicated by p_frame# assertion. write data is stable a nd valid when p_irdy# is asserted and read data is stable and valid when p_trdy# is asserted. data is transferred on rising clock edges when both p_irdy# and p_trdy# are asserted. during bus idle, PI7C7300D drives p_ad to a valid logic level when p_gnt# is asserted. p_cbe[3:0] v9, u12, u16, v19 pb primary command/byte enables. multiplexed command field and byte enable field. during address phase, the initiator drives th e transaction type on these pins. the initiator then driv es the byte enables during data phases. during bus idle, PI7C7300D drives p_cbe[3:0] to a valid logi c level when p_gnt# is asserted. p_par u15 pb primary parity. parity is even across p_ad[31:0], p_cbe[3:0], and p_par (i.e. an even number of 1?s). p_par is an input and is valid and stable one cycle after the address phase (indicated by assertion of p_frame#) for address parity. for write data phases, p_par is an input and is valid one clock after p_irdy# is asserted. for read data phase, p_par is an output and is valid one clock after p_trdy# is asserted. signal p_par is tri-stated one cycle after the p_ad lines are tri-stated. during bus idle, PI7C7300D drives p_par to a valid l ogic level when p_gnt# is asserted. p_frame# w13 psts primary frame (active low). driven by the initiator of a transaction to indicate the beginning and duration of an access. the de-assertion of p_frame# indicates the final data phase requested by the initiator. before being tri-stated, it is driven to a de-asserted state for one cycle.
PI7C7300D 3-port pci-to-pci bridge page 14 of 107 pericom semiconductor november 2005 - revision 1.01 name pin # type description p_irdy# v13 psts primary irdy (active low). driven by the initiator of a transaction to indicate its ability to complete current data phase on the primary side. once asserted in a data phase, it is not de-asserted until the end of the data phase. before tri-stated, it is driven to a de-asserted state for one cycle. p_trdy# u13 psts primary trdy (active low). driven by the target of a transaction to indicat e its ability to complete current data phase on the primary side. once asserted in a data phase, it is not de-asserted until the end of the data phase. before tri-stated, it is driven to a de-asserted state for one cycle. p_devsel# y14 psts primary device select (active low). asserted by the target indicating that the device is accepting the transaction. as a master, PI7C7300D waits for the assertion of this signal with in 5 cycles of p_frame# assertion; otherwise, terminate with master abort. before tri-stated, it is driven to a de-asserted state for one cycle. p_stop# w14 psts primary stop (active low). asserted by the target indicating that the target is requesting the initiator to stop the current transaction. before tri-stated, it is driven to a de-asserted state for one cycle. p_lock# v14 psts primary lock (active low). asserted by the master for multiple transactions to complete. p_idsel y10 pi primary id select. used as a chip select line for type 0 configuration accesses to PI7C7300D configuration space. p_perr# y15 psts primary parity error (active low). asserted when a data parity error is detected for data received on the primary interface. before being tri-stated, it is driven to a de-asserted state for one cycle. p_serr# w15 pod primary system error (active low). can be driven low by any device to indicate a system error condition. PI7C7300D drives this pin on: address parity error posted write data parity error on target bus secondary s1_serr# or s2_serr# asserted master abort during posted write transaction target abort during posted write transaction posted write transaction discarded delayed write request discarded delayed read request discarded delayed transaction master timeout this signal requires an external pull-up resistor for proper operation. p_req# w6 pts primary request (active low). this is asserted by PI7C7300D to indicate that it wants to start a transaction on the primary bus. PI7C7300D de-asserts this pin for at least 2 pci clock cycles before asserting it again. p_gnt# u7 pi primary grant (active low). when asserted, PI7C7300D can access the primary bus. during idle and p_gnt# asserted, PI7C7300D will drive p_ad, p_cbe, and p_par to valid logic levels. p_reset# y5 pi primary reset (active low). when p_reset# is active, all pci signals should be asynchronously tri-stated.
PI7C7300D 3-port pci-to-pci bridge page 15 of 107 pericom semiconductor november 2005 - revision 1.01 name pin # type description p_m66en v18 pi primary interface 66mhz operation. this input is used to specify if PI7C7300D is capable of running at 66mhz. for 66mhz operation on the primary bus, this signal should be pulled ?high?. for 33mhz operation on the primary bus, this signal should be pulled ?low?. in this condition, s1_m66en and s2_m66en w ill both need to be ?low?, forcing both secondary buses to run at 33mhz also. 3.3 secondary bus interface signals name pin # type description s1_ad[31:0], s2_ad[31:0] b20, b19, c20, c19, c18, d20, d19, d17, e19, e18, e17, f20, f19, f17, g20, g19, l20, l19, l18, m20, m19, m17, n20, n19, n18, n17, p17, r20, r19, r18, t20, t19 j4, h1, h2, h3, h4, g1, g3, g4, f2, f3, f4, e1, e4, d1, c1, b1, c5, b5, d6, c6, b6, a6, c7, b7, d8, c8, d9, c9, b9, a9, d10, c10 pb secondary address/data. multiplexed address and data bus. address is i ndicated by s1_frame# or s2_frame# assertion. write data is stable and valid when s1_irdy# or s2_irdy# is asserted and read data is stable and valid when s1_irdy# or s2_irdy# is asserted. data is transferred on rising clock edges when both s1_irdy# or s2_irdy# and s1_trdy# or s2_trdy# are asserted. during bus idle, PI7C7300D drives s1_ad or s2_ad to a valid logic level when s1_gnt# or s2_gnt# is asserted respectively. s1_cbe[3:0], s2_cbe[3:0] e20, g18, k17, p20 f1, a1, a4, a7 pb secondary command/byte enables. multiplexed command field and byte enable field. during address phase, the initiator drives th e transaction type on these pins. the initiator then driv es the byte enables during data phases. during bus idle, PI7C7300D drives s1_cbe[3:0] or s2_cbe[3:0 ] to a valid logic level when the internal grant is asserted. s1_par, s2_par k18, b4 pb secondary parity. parity is even across s1_ad[31:0], s1_cbe[3:0], and s1_par or s2_ad[31:0], s2_cbe[3:0], and s2_par (i.e. an even number of 1?s). s1_par or s2_par is an input and is valid and stable one cycle after the address phase (indicated by assertion of s1_frame# or s2_frame#) for address parity. for write data phases, s1_par or s2_par is an input and is valid one clock after s1_irdy# s2_irdy# is asserted. for read data phase, s1_par or s2_par is an output and is valid one clock after s1_trdy# or s2_trdy# is asserted. signal s1_par or s2_par is tri-stated one cycle after the s1_ad or s2_ad lines are tri-stated. during bus idle, PI7C7300D drives s1_par or s2_par to a valid logic level when the internal grant is asserted. s1_frame#, s2_frame# h20, d2 psts secondary frame (active low). driven by the initiator of a transaction to indicate the beginning and duration of an access. the de-assertion of s1_frame# or s2_frame# i ndicates the final data phase requested by the initiator. before being tri- stated, it is driven to a de-asserted state for one cycle.
PI7C7300D 3-port pci-to-pci bridge page 16 of 107 pericom semiconductor november 2005 - revision 1.01 name pin # type description s1_irdy#, s2_irdy# h19, b2 psts secondary irdy (active low). driven by the initiator of a transaction to indicate its ability to complete current data phase on the secondary side. once asserted in a data phase, it is not de-asserted until the end of the data phase. be fore tri-stated, it is driven to a de-asserted state for one cycle. s1_trdy#, s2_trdy# h18, a2 psts secondary trdy (active low). driven by the target of a transaction to i ndicate its ability to complete current data phase on the secondary side. once asserted in a data phase, it is not de-asserted until the end of the data phase. before tri-stated, it is driven to a de-asserted state for one cycle. s1_devsel#, s2_devsel# j20, d3 psts secondary device select (active low). asserted by the target indicating that the device is accepting the transaction. as a master, PI7C7300D waits for the assertion of this signal within 5 cycles of s1_frame# or s2_frame# assertion; otherwise, terminate with master abort. before tri-stated, it is driven to a de- asserted state for one cycle. s1_stop#, s2_stop# j19, c3 psts secondary stop (active low). asserted by the target indicating that the target is requesting the initiator to stop the current transaction. before tri- stated, it is driven to a de-asserted state for one cycle. s1_lock#, s2_lock# j18, b3 psts secondary lock (active low). asserted by the master for multiple transactions to complete. s1_perr#, s2_perr# j17, d4 psts secondary parity e rror (active low). asserted when a data parity error is detected for data received on the secondary interface. before being tri-stated, it is driven to a de-asserted state for one cycle. s1_serr#, s2_serr# k20, c4 pi secondary system e rror (active low). can be driven low by any device to indicate a system error condition. s1_req#[7:0], s2_req#[6:0] b11, a12, d13, c13, c15, a16, c17, b17 r3, p2, p1, m2, m1, k1, k3 piu secondary request (active low). this is asserted by an external device to indicate that it wants to start a transaction on the secondary bus. the input is externally pulled up through a resistor to vdd. s1_gnt#[7:0] s2_gnt#[6:0] c11, b12, b13, a14, d14, b16, d16, b18 p4, r1, n4, m3, l4, l1, k2 po secondary grant (active low). PI7C7300D asserts this pin to access the secondary bus. PI7C7300D de- asserts this pin for at least 2 pci clock cycles before asserting it again. during idle and s1_gnt# or s2- gnt# asserted, PI7C7300D will drive s1_ad, s1_cbe, and s1_par or s2_ad, s2_cbe, and s2_par. s1_reset#, s2_reset# b10, t4 po secondary reset (active low). asserted when any of the following conditions are met: 1. signal p_reset# is asserted. 2. secondary reset bit in bridge control register in configuration space is set. when asserted, all control signals are tri-stated and zeroes are driven on s1_ad, s1_cbe, and s1_par or s2_ad, s2_cbe, and s2_par. s1_en, s2_en w3, w4 piu secondary enable (active high). when s1_en or s2_en is inactive, secondary bus pci s1 or pci s2 will be asynchronously tri-stated. s1_m66en, s2_m66en d7, w5 pi secondary interfa ce 66mhz operation. this input is used to specify if PI7C7300D is capable of running at 66mhz on the secondary side. when high, the s1 or s2 bus may run at 66mhz. when low, the s1 or s2 bus may only run at 33mhz. if p_m66en is pulled low, both s1_m66en and s2_m66en need to be low.
PI7C7300D 3-port pci-to-pci bridge page 17 of 107 pericom semiconductor november 2005 - revision 1.01 name pin # type description s_cfn# y2 piu secondary bus central function control pin. when tied low, it enables the inte rnal arbiter. when tied high, an external arbiter must be used. s1_req#[0] or s2_req#[0] is reconfigured to be the secondary bus grant input, and s1_gnt#[0] or s2_gnt#[0] is reconfigured to be the secondary bus request output. 3.4 clock signals name pin # type description p_clk v6 pi primary clock input. provides timing for all transactions on the primary interface. s1_clkout [7:0] a11, c12, a13, b14, b15, c16, a18, a19 pts secondary clock output. provides secondary 1 clocks phase synchronous with the p_clk. s2_clkout [7:0] t3, t1, p3, n3, m4, l3, l2, j1 pts secondary clock output. provides secondary 2 clocks phase synchronous with the p_clk. 3.5 miscellaneous signals name pin # type description by_pass y4 pi reserved. reserved for future use. must be tied high. pll_tm y3 pi reserved. reserved for future use. must be tied low. s_clkin v5 pi reserved. reserved for future use. must be tied low. scan_tm# v4 pi full-scan test mode enable (active low). connect high for normal operation. when scan_tm# is active, th e ten scan chains will be enabled. the scan clock is p_clk. the scan input and outputs are as follows: s1_req[6], s1_req[5], s1_req[4], s1_req[3], s1_req[2], s2_req#[6], s2_req#[5], s2_req#[4], s2_req#[3], s2_req#[2], and s1_gnt#[6], s1_gnt#[5], s1_gnt#[4], s1_gnt#[3], s1_gnt#[2], s2_gnt#[6], s2_gnt#[5], s2_gnt#[4], s2_gnt#[3], s2_gnt#[2] scan_en u5 pid full-scan enable control. scan_en should be tied low in normal mode. when scan_en is low, full- scan is in shift operation if scan_tm# is active. when scan_en is high, fu ll-scan is in parallel operation if scan_tm# is active. 3.6 compact pci hot-swap signals name pin # type description loo u1 po hot swap led . the output of this pin lights a blue led to indicate insertion and removal ready status. if hs_en is low, pin is s2_gnt#[7]. hs_sw# t2 pi hot swap switch. when driven low, this signal indicates that the board ejector handle indicates an insertion or impending extraction of a board. if hs_en is low, pin is s2_req#[7].
PI7C7300D 3-port pci-to-pci bridge page 18 of 107 pericom semiconductor november 2005 - revision 1.01 name pin # type description hs_en u6 pi hot swap enable. to enable hot swap friendly support, this signal should be pulled high. enum# r4 pod hot swap status indicator. the output of enum# indicates to the system that an insertion has occurred of that an extraction is about to occur. 3.7 jtag boundary scan signals name pin # type description tck v2 piu test clock. used to clock state information and data into and out of the PI7C7300D during boundary scan. tms w1 piu test mode select. used to control the state of the test access port controller. tdo v3 pts test data output. when scan_en is high, it is used (in conjunction with tck) to shift data out of the test access port (tap) in a serial bit stream. tdi w2 piu test data input. when scan_en is high, it is used (in conjunction with tck) to shift data and instructions into the test access port (t ap) in a serial bit stream. trst# u3 piu test reset. active low signal to reset the test access port (tap) controller into an initialized state. 3.8 power and ground name pin # type description vdd b8, c14, d5, d11, d15, e2, f18, j3, l17, n2, p19, u10, v1, v7, v15, w20 3.3v digital power vss a3, a5, a8, a10, a15, a17, a20, c2, d12, d18, e3, g2, g17, h17, j2, j9, j10, j11, j12, k4, k9, k10, k11, k12, k19, l9, l10, l11, l12, m9, m10, m11, m12, m18, n1, p18, r2, t18, u2, u9, u14, u17, v17, w11, y6, y13 digital ground avcc y1 analog 3.3v for pll agnd u4 analog ground for pll 3.9 PI7C7300D pbga pin list pin # name type pin # name type a1 s2_cbe[2] pb a2 s2_trdy# psts a3 vss - a4 s2_cbe[1] pb a5 vss - a6 s2_ad[10] pb
PI7C7300D 3-port pci-to-pci bridge page 19 of 107 pericom semiconductor november 2005 - revision 1.01 pin # name type pin # name type a7 s2_cbe[0] pb a8 vss - a9 s2_ad[2] pb a10 vss - a11 s1_clkout[7] pts a12 s1_req#[6] piu a13 s1_clkout[5] pts a14 s1_gnt#[4] po a15 vss - a16 s1_req#[2] piu a17 vss - a18 s1_clkout[1] pts a19 s1_clkout[0] pts a20 vss - b1 s2_ad[16] pb b2 s2_irdy# psts b3 s2_lock# psts b4 s2_par pb b5 s2_ad[14] pb b6 s2_ad[11] pb b7 s2_ad[8] pb b8 vdd - b9 s2_ad[3] pb b10 s1_reset# po b11 s1_req#[7] piu b12 s1_gnt#[6] po b13 s1_gnt#[5] po b14 s1_clkout[4] pts b15 s1_clkout[3] pts b16 s1_gnt#[2] po b17 s1_req#[0] piu b18 s1_gnt#[0] po b19 s1_ad[30] pb b20 s1_ad[31] pb c1 s2_ad[17] pb c2 vss - c3 s2_stop# psts c4 s2_serr# pi c5 s2_ad[15] pb c6 s2_ad[12] pb c7 s2_ad[9] pb c8 s2_ad[6] pb c9 s2_ad[4] pb c10 s2_ad[0] pb c11 s1_gnt#[7] po c12 s1_clkout[6] pts c13 s1_req#[4] piu c14 vdd pts c15 s1_req#[3] piu c16 s1_clkout[2] pts c17 s1_req#[1] piu c18 s1_ad[27] pb c19 s1_ad[28] pb c20 s1_ad[29] pb d1 s2_ad[18] pb d2 s2_frame# psts d3 s2_devsel# psts d4 s2_perr# psts d5 vdd - d6 s2_ad[13] pb d7 s1_m66en pi d8 s2_ad[7] pb d9 s2_ad[5] pb d10 s2_ad[1] pb d11 vdd - d12 vss - d13 s1_req#[5] piu d14 s1_gnt#[3] po d15 vdd - d16 s1_gnt#[1] po d17 s1_ad[24] pb d18 vss - d19 s1_ad[25] pb d20 s1_ad[26] pb e1 s2_ad[20] pb e2 vdd - e3 vss - e4 s2_ad[19] pb e17 s1_ad[21] pb e18 s1_ad[22] pb e19 s1_ad[23] pb e20 s1_cbe[3] pb f1 s2_cbe[3] pb f2 s2_ad[23] pb f3 s2_ad[22] pb f4 s2_ad[21] pb f17 s1_ad[18] pb f18 vdd - f19 s1_ad[19] pb f20 s1_ad[20] pb g1 s2_ad[26] pb g2 vss - g3 s2_ad[25] pb g4 s2_ad[24] pb g17 vss - g18 s1_cbe[2] pb g19 s1_ad[16] pb g20 s1_ad[17] pb h1 s2_ad[30] pb h2 s2_ad[29] pb h3 s2_ad[28] pb h4 s2_ad[27] pb h17 vss - h18 s1_trdy# psts h19 s1_irdy# psts h20 s1_frame# psts j1 s2_clkout[0] pts j2 vss - j3 vdd - j4 s2_ad[31] pb j9 vss - j10 vss - j11 vss - j12 vss - j17 s1_perr# psts j18 s1_lock# psts j19 s1_stop# psts j20 s1_devsel# psts k1 s2_req#[1] piu k2 s2_gnt#[0] po
PI7C7300D 3-port pci-to-pci bridge page 20 of 107 pericom semiconductor november 2005 - revision 1.01 pin # name type pin # name type k3 s2_req#[0] piu k4 vss - k9 vss - k10 vss - k11 vss - k12 vss - k17 s1_cbe[1] pb k18 s1_par pb k19 vss - k20 s1_serr# pi l1 s2_gnt#[1] po l2 s2_clkout[1] pts l3 s2_clkout[2] pts l4 s2_gnt#[2] po l9 vss - l10 vss - l11 vss - l12 vss - l17 vdd - l18 s1_ad[13] pb l19 s1_ad[14] pb l20 s1_ad[15] pb m1 s2_req#[2] piu m2 s2_req#[3] piu m3 s2_gnt#[3] po m4 s2_clkout[3] pts m9 vss - m10 vss - m11 vss - m12 vss - m17 s1_ad[10] pb m18 vss - m19 s1_ad[11] pb m20 s1_ad[12] pb n1 vss - n2 vdd - n3 s2_clkout[4] pts n4 s2_gnt#[4] po n17 s1_ad[6] pb n18 s1_ad[7] pb n19 s1_ad[8] pb n20 s1_ad[9] pb p1 s2_req#[4] piu p2 s2_req#[5] piu p3 s2_clkout[5] pts p4 s2_gnt#[6] po p17 s1_ad[5] pb p18 vss - p19 vdd - p20 s1_cbe[0] pb r1 s2_gnt#[5] po r2 vss - r3 s2_req#[6] piu r4 enum# pod r17 p_ad[0] pb r18 s1_ad[2] pb r19 s1_ad[3] pb r20 s1_ad[4] pb t1 s2_clkout[6] pts t2 hs_sw pi t3 s2_clkout[7] pts t4 s2_reset# po t17 p_ad[1] pb t18 vss - t19 s1_ad[0] pb t20 s1_ad[1] pb u1 loo po u2 vss - u3 trst# piu u4 agnd - u5 scan_en pid u6 hs_en pi u7 p_gnt# pi u8 p_ad[26] pb u9 vss - u10 vdd - u11 p_ad[19] pb u12 p_cbe[2] pb u13 p_trdy# pb u14 vss - u15 p_par pb u16 p_cbe[1] pb u17 vss - u18 p_ad[10] pb u19 p_ad[7] pb u20 p_ad[4] pb v1 vdd - v2 tck piu v3 tdo pts v4 scan_tm# pi v5 s_clkin pi v6 p_clk pi v7 vdd - v8 p_ad[27] pb v9 p_cbe[3] pb v10 p_ad[22] pb v11 p_ad[20] pb v12 p_ad[16] pb v13 p_irdy# pb v14 p_lock# psts v15 vdd - v16 p_ad[15] pb v17 vss - v18 p_m66en# pi v19 p_cbe[0] pb v20 p_ad[3] pb w1 tms piu w2 tdi piu w3 s1_en piu w4 s2_en piu w5 s2_m66en pi w6 p_req# pts w7 p_ad[30] pb w8 p_ad[28] pb w9 p_ad[24] pb w10 p_ad[23] pb w11 vss - w12 p_ad[17] pb w13 p_frame# pb w14 p_stop# psts
PI7C7300D 3-port pci-to-pci bridge page 21 of 107 pericom semiconductor november 2005 - revision 1.01 pin # name type pin # name type w15 p_serr# pod w16 p_ad[14] pb w17 p_ad[12] pb w18 p_ad[9] pb w19 p_ad[6] pb w20 vdd - y1 avcc - y2 s_cfn# piu y3 pll_tm pi y4 bypass - y5 p_reset# pi y6 vss - y7 p_ad[31] pb y8 p_ad[29] pb y9 p_ad[25] pb y10 p_idsel pi y11 p_ad[21] pb y12 p_ad[18] pb y13 vss - y14 p_devsel# psts y15 p_perr# psts y16 p_ad[13] pb y17 p_ad[11] pb y18 p_ad[8] pb y19 p_ad[5] pb y20 p_ad[2] pb 4 pci bus operation this chapter offers information about pci transactions, transaction forwarding across PI7C7300D, and transaction termination. the PI7C7300D has three 128-byte buffers for buffering of upstream and downstream trans actions. these hold addresses, data, commands, and byte enables and are used for both read and write transactions. 4.1 types of transactions this section provides a summary of pci transactions performed by PI7C7300D. table 4-1 lists the command code and name of each pci transaction. the master and target columns indicate support for each transaction when PI7C7300D initiates transactions as a master, on the primary (p) and secondary (s1, s2) buses, and when PI7C7300D responds to transactions as a target, on the primary (p) and secondary (s1, s2) buses. table 4-1 pci transactions types of transactions initiates as master responds as target primary secondary primary secondary 0000 interrupt acknowledge n n n n 0001 special cycle y y n n 0010 i/o read y y y y 0011 i/o write y y y y 0100 reserved n n n n 0101 reserved n n n n 0110 memory read y y y y 0111 memory write y y y y 1000 reserved n n n n 1001 reserved n n n n 1010 configuration read n y y n 1011 configuration write y (type 1 only) y y y (type 1 only) 1100 memory read multiple y y y y 1101 dual address cycle y y y y 1110 memory read line y y y y 1111 memory write and invalidate y y y y
PI7C7300D 3-port pci-to-pci bridge page 22 of 107 pericom semiconductor november 2005 - revision 1.01 as indicated in table 4-1 , the following pci commands are not supported by PI7C7300D: PI7C7300D never initiates a pci transaction with a reserved command code and, as a target, PI7C7300D ignores reserved command codes. PI7C7300D does not generate interrupt acknowledge transactions. PI7C7300D ignores interrupt acknowledge transactions as a target. PI7C7300D does not respond to special cycle transactions. PI7C7300D cannot guarantee delivery of a special cycle trans action to downstream buses because of the broadcast nature of the special cycle command and the inability to control the transaction as a target. to generate speci al cycle transactions on other pci buses, either upstream or downstream, type 1 configuration write must be used. PI7C7300D neither generates type 0 configuration transactions on the primary pci bus nor responds to type 0 configuration transactions on the secondary pci buses. 4.2 single address phase a 32-bit address uses a single address phase. this address is driven on p_ad[31:0], and the bus command is driven on p_cbe[3:0]. PI7C7300D supports the linear increment address mode only, which is indicated when the lowest two address bits are equal to zero. if either of the lowest two address bits is nonzero, PI7C7300D automatically disconnects the transaction after the first data transfer. 4.3 dual address phase a 64-bit address uses two address phases. the first address phase is denoted by the asserting edge of frame#. the sec ond address phase always follows on the next clock cycle. for a 32-bit interface, the first address phase contains dual address command code on the c/be#[3:0] lines, and the low 32 address bits on the ad[31:0] lines. the second address phase consists of the specific memory transaction command code on the c/be#[3:0] lines, and the high 32 address bits on the ad[31:0] lines. in this way, 64-bit addressing can be supported on 32-bit pci buses. the pci-to-pci bridge architecture specification supports the use of dual address transactions in the prefetchable memory range only. see section 5.3.2 for a discussion of prefetchable address space. the PI7C7300D supports dual address transactions in both the upstream and the downstream direction. the PI7C7300D supports a programmable 64-bit address range in prefetchable memory for downstream forwarding of dual address transactions. dual address transactions falli ng outside the prefetchable address range are forwarded upstream, but not downstream. prefetching and posting are performed in a manner consistent with the guidelines given in this specification for each type of memory transaction in prefetchable memory space.
PI7C7300D 3-port pci-to-pci bridge page 23 of 107 pericom semiconductor november 2005 - revision 1.01 4.4 device select (devsel#) generation PI7C7300D always performs positive addr ess decoding (medium decode) when accepting transactions on either the primar y or secondary buses . PI7C7300D never does subtractive decode. 4.5 data phase the address phase of a pci transaction is followed by one or more data phases. a data phase is completed when irdy# a nd either trdy# or stop# are asserted. a transfer of data occurs only when both irdy# and trdy# are asserted during the same pci clock cycle. the last data phase of a transaction is indicated when frame# is de-asserted and both trdy# and irdy# are asserted, or when irdy# and stop# are asserted. see section 4.9 for further discussion of transaction termination. depending on the command type, PI7C7300D can support multiple data phase pci transactions. for detailed descriptions of how PI7C7300D imposes disconnect boundaries, see section 4.6.4 for write addre ss boundaries and section 4.7.3 read address boundaries. 4.6 write transactions write transactions are treated as either posted write or delayed write transactions. table 4-2 shows the method of forwarding used for each type of write operation. table 4-2 write transaction forwarding type of transaction type of forwarding memory write posted (except vga memory) memory write and invalidate posted memory write to vga memory delayed i/o write delayed type 1 configuration write delayed
PI7C7300D 3-port pci-to-pci bridge page 24 of 107 pericom semiconductor november 2005 - revision 1.01 4.6.1 memory write transactions posted write forwarding is used for ?memory write? and ?memory write and invalidate? transactions. when PI7C7300D determines that a memory write transaction is to be forwarded across the bridge, PI7C7300D asserts devsel# with medium timing and trdy# in the next cycle, provided that enough buffer space is av ailable in the posted memory write queue for the address and at least one dword of data. under this condition, PI7C7300D accepts write data without obtaining access to the target bus. the PI7C7300D can accept one dword of write data every pci clock cycle. that is, no ta rget wait state is inserted. the write data is stored in an internal posted write buffers and is subsequently delivered to the target. the PI7C7300D continues to accept write data until one of the following events occurs: the initiator terminates the transaction by de-asserting frame# and irdy#. an internal write address boundary is reached, such as a cache line boundary or an aligned 4kb boundary, depending on the transaction type. the posted write data buffer fills up. when one of the last two events occurs, the PI7C7300D returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. once the posted write data moves to the head of the posted data queue, PI7C7300D asserts its request on the target bus. this can occur while PI7C7300D is still receiving data on the initiator bus. when the grant for the target bus is received and the target bus is detected in the idle condition, PI7C7300D asserts frame# and drives the stored write address out on the target bus. on the following cycle, PI7C7300D drives the first dword of write data and continues to transfer write data until all write data corresponding to that transaction is delivered, or until a target termination is received. as long as write data exists in the queue, PI7C7300D can drive one dword of write data each pci clock cycle; that is, no master wait st ates are inserted. if write data is flowing through PI7C7300D and the initiator stalls, pi7c 7300d will signal the last data phase for the current transaction at the target bus if the queue empties. PI7C7300D will restart the follow-on transactions if the queue has new data. PI7C7300D ends the transaction on the target bus when one of the following conditions is met: all posted write data has been delivered to the target. the target returns a target disconnect or target retry (PI7C7300D starts another transaction to deliver the rest of the write data). the target returns a target abort (PI7C7300D discards remaining write data). the master latency timer expires, and PI7C7300D no longer has the target bus grant (PI7C7300D starts another transaction to deliver remaining write data). section 4.9.3.2 provides detailed information about how PI7C7300D responds to target termination during posted write transactions.
PI7C7300D 3-port pci-to-pci bridge page 25 of 107 pericom semiconductor november 2005 - revision 1.01 4.6.2 memory write and invalidate transactions posted write forwarding is used for memory write and invalidate transactions. the PI7C7300D disconnects memory write a nd invalidate commands at aligned cache line boundaries. the cache line size value in th e cache line size register gives the number of dword in a cache line. if the value in the cache line size register does meet the memory write and invalidate conditions, the PI7C7300D returns a target di sconnect to the initia tor either on a cache line boundary or when the posted write buffer fills. when the memory write and invalidate tran saction is disconnected before a cache line boundary is reached, typically because the posted write buffer fills, the trans-action is converted to memory write transaction. 4.6.3 delayed write transactions delayed write forwarding is used for i/o wr ite transactions and type 1 configuration write transactions. a delayed write transaction guarantees that the actual target response is returned back to the initiator without holding the initiating bus in wait states. a delayed write transaction is limited to a single dword data transfer. when a write transaction is first detected on the initiator bus, and PI7C7300D forwards it as a delayed transaction, PI7C7300D clai ms the access by asserting devsel# and returns a target retry to th e initiator. during the address phase, PI7C7300D samples the bus command, address, and address parity one cycle later. after irdy# is asserted, PI7C7300D also samples the first data dword, byte enable bits, and data parity. this information is placed into the delayed tran saction queue. the transaction is queued only if no other existing delayed transactions have the same address and command, and if the delayed transaction queue is not full. when the delayed write transaction moves to the head of the delayed transaction queue and a ll ordering constraints with posted data are satisfied. the PI7C7300D initiates the tran saction on the target bus. PI7C7300D transfers the write data to the target. if PI7C7300D receives a target retry in response to the write transaction on the target bus, it continues to repeat the write transaction until the data transf er is completed, or until an error condition is encountered. if PI7C7300D is unable to deliver write data after 2 24 (default) or 2 32 (maximum) attempts, PI7C7300D will report a system erro r. PI7C7300D also asserts p_serr# if the primary serr# enable bit is set in the command register. see section 7.4 for information on the assertion of p_serr#. when the initiator repeats the same write transaction (same command, address, byte enable bits, and data), and the completed delayed transaction is at the head of the queue, the PI7C7300D cl aims the access by asserting devsel# and returns trdy# to the initiator, to indicate that the write data was transferred. if the initiator requests multiple dword, PI7C7300D also asserts stop# in conjunction with trdy# to signal a target disconnect. note that only those
PI7C7300D 3-port pci-to-pci bridge page 26 of 107 pericom semiconductor november 2005 - revision 1.01 bytes of write data with valid byte enable bits are compared. if any of the byte enable bits are turned off (driven high), the corresponding byte of write data is not compared. if the initiator repeats the write transaction before the data has been transferred to the target, PI7C7300D returns a target retry to th e initiator. PI7C7300D continues to return a target retry to the initiator until write data is delivered to the target, or until an error condition is encountered. when the write transaction is repeated, PI7C7300D does not make a new entry into the delayed transaction queue. section 4.9.3.1 provides detailed information about how PI7C7300D responds to target termination during delayed write transactions. PI7C7300D implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction completion queue. the initial value of this timer can be set to the retry counter register offset 78h. if the initiator does not repeat the delayed write transaction before the discard timer expires, PI7C7300D discards the delayed write completion from the delayed transaction completion queue. PI7C7300D also conditi onally asserts p_serr# (see section 7.4 ). 4.6.4 write transaction address boundaries PI7C7300D imposes internal address boundaries when accepting write data. the aligned address boundaries are used to prevent PI7C7300D from continuing a transaction over a device address boundary and to provide an upper limit on maximum latency. PI7C7300D returns a target disconnect to the initiator when it reaches the aligned address boundaries under conditions shown in table 4?3. table 4-3 write transactio n disconnect address boundaries type of transaction conditi on aligned address boundary delayed write all disconnects after one data transfer posted memory write memory write disconnect control bit = 0 (1) 4kb aligned address boundary posted memory write memory write disconnect control bit = 1 (1) disconnects at cache line boundary posted memory write and invalidate cache line size 1, 2, 4, 8, 16 4kb aligned address boundary posted memory write and invalidate cache line size = 1, 2, 4, 8, 16 cache line boundary if posted memory write data fifo does not have enough space for the cache line note 1. memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the configuration space. 4.6.5 buffering multiple write transactions PI7C7300D continues to accept posted memory wr ite transactions as long as space for at least one dword of data in the posted write data buffer remains. if the posted write data buffer fills before the initiator terminat es the write transaction, PI7C7300D returns a target disconnect to the initiator.
PI7C7300D 3-port pci-to-pci bridge page 27 of 107 pericom semiconductor november 2005 - revision 1.01 delayed write transactions are posted as long as at least one open entry in the delayed transaction queue exists. therefore, severa l posted and delayed write transactions can exist in data buffers at the same time. see chapter 6 for information about how multiple posted and delayed write transactions are ordered. 4.6.6 fast back-to-back write transactions PI7C7300D can recognize and post fast back-to-back write transactions. when PI7C7300D cannot accept the second transacti on because of buffer space limitations, it returns a target retry to the initiator. the fast back-to-back enable bit must be set in the command register for upstream write transactions, and in the bridge control register for downstream write transactions. 4.7 read transactions delayed read forwarding is used for all read transactions crossing PI7C7300D. delayed read transactions are treated as eith er prefetchable or non-prefetchable. table 4-4 shows the read behavior, prefetchable or non-prefet chable, for each type of read operation. 4.7.1 prefetchable read transactions a prefetchable read transaction is a read transaction where PI7C7300D performs speculative dword reads, transferring data from the target before it is requested from the initiator. this behavior allows a prefetchable read transaction to consist of multiple data transfers. however, byte enable bits cannot be forwarded for all data phases as is done for the single data phase of the non-prefet chable read transaction. for prefetchable read transactions, PI7C7300D forces all byte enable bits to be turned on for all data phases. prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for memory read tran sactions that fall into prefetchable memory space. the amount of data that is pre-fetc hed depends on the type of transaction. the amount of pre-fetching may also be affected by the amount of free buffer space available in PI7C7300D, and by any read address boundaries encountered. pre-fetching should not be used for those read transactions that have side effects in the target device, that is, control and status registers, fifos, and so on. the target device?s base address register or registers indicate if a memory address region is prefetchable. 4.7.2 non-prefetchable read transactions a non-prefetchable read transaction is a read transaction where PI7C7300D requests one and only one dword from the target and disconnects the initiator after delivery of the first dword of read data. unlike prefetchable read transactions, PI7C7300D forwards the read byte enable information for the data phase.
PI7C7300D 3-port pci-to-pci bridge page 28 of 107 pericom semiconductor november 2005 - revision 1.01 non-prefetchable behavior is used for i/o a nd configuration read transactions, as well as for memory read transactions that fa ll into non-prefetchable memory space. if extra read transactions could have side effects, for example, when accessing a fifo, use non-prefetchable read transactions to those locations. accordingly, if it is important to retain the value of the byte enable bits during the data phase, use non-prefetchable read transactions. if these locations are ma pped in memory space, use the memory read command and map the target into non-prefet chable (memory-mapped i/o) memory space to use non-prefetching behavior. 4.7.3 read prefetch address boundaries PI7C7300D imposes internal read address boundaries on read pre-fetched data. when a read transaction reaches one of these a ligned address boundaries , the PI7C7300D stops pre-fetched data, unless the target signals a ta rget disconnect before the read pre-fetched boundary is reached. when PI7C7300D finishes transferring this read data to the initiator, it returns a target disconnect with the last data transfer, unless the initiator completes the transaction before all pre-fetched read data is delivered. any leftover pre- fetched data is discarded. prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4kb address boundary, or until the initiator de-asserts frame#. section 4.7.6 describes flow- through mode during read operations.
PI7C7300D 3-port pci-to-pci bridge page 29 of 107 pericom semiconductor november 2005 - revision 1.01 table 4-5 shows the read pre-fetch address boundaries for read transactions during non- flow-through mode. table 4-4 read prefetch address boundaries type of transaction address space cache line size (cls) prefetch aligned address boundary configuration read - * one dword (no prefetch) i/o read - * one dword (no prefetch) memory read non-prefetchable * one dword (no prefetch) memory read prefetchable cls = 0 or 16 16-dword aligned address boundary memory read prefetchable cls = 1, 2, 4, 8, 16 cache line address boundary memory read line - cls = 0 or 16 16-dword aligned address boundary memory read line - cls = 1, 2, 4, 8, 16 cache line boundary memory read multiple - cls = 0 or 16 32-dword a ligned address boundary memory read multiple - cls = 1, 2, 4, 8, 16 2x of cache line boundary - does not matter if it is prefetchable or non-prefetchable * don?t care
PI7C7300D 3-port pci-to-pci bridge page 30 of 107 pericom semiconductor november 2005 - revision 1.01 table 4-5 read transaction prefetching type of transaction read behavior i/o read prefetching never allowed configuration read prefetching never allowed downstream: prefetching used if address is prefetchable space memory read upstream: prefetching used or programmable memory read line prefetching always used memory read multiple pr efetching always used see section 5.3 for detailed information about prefetch able and non-prefetchable address spaces. 4.7.4 delayed read requests PI7C7300D treats all read transactions as delayed read transactions, which means that the read request from the initiator is posted into a delayed transaction queue. read data from the target is placed in the read data queue directed toward the initiator bus interface and is transferred to the initiator when the initiator repeats the read transaction. when PI7C7300D accepts a delayed read request, it first samples the read address, read bus command, and address parity. when irdy# is asserted, PI7C7300D then samples the byte enable bits for the first data phase. this information is entered into the delayed transaction queue. PI7C7300D terminates the transaction by signaling a target retry to the initiator. upon reception of the ta rget retry, the initiator is re quired to continue to repeat the same read transaction until at least one data transfer is completed, or until a target response (target abort or master abort) other than a target retry is received. 4.7.5 delayed read completion with target when delayed read request reaches the head of the delayed transaction queue, PI7C7300D arbitrates for the target bus and initiates the read transaction only if all previously queued posted write transactions have been delivered. PI7C7300D uses the exact read address and read command captured from the initiator during the initial delayed read request to initiate the read tr ansaction. if the read transaction is a non- prefetchable read, PI7C7300D drives the captured byte enable bits during the next cycle. if the transaction is a prefetchab le read transaction, it drives all byte enable bits to zero for all data phases. if PI7C7300D receives a target retry in response to the read transaction on the target bus, it continues to repeat the read transaction until at least one data transfer is completed, or until an erro r condition is encountered. if the transaction is terminated via normal master termination or target disconnect after at least one data transfer has been completed, PI7C7300D does not initiate any further attempts to read more data. if PI7C7300D is unable to obtain read data from the target after 2 24 (default) or 2 32 (maximum) attempts, PI7C7300D will report a sy stem error. the number of attempts is programmable. PI7C7300D also asserts p_serr# if the primary serr# enable bit is set in the command register. see section 7.4 for information on the assertion of p_serr#. once PI7C7300D receives devsel# and trdy# from the target, it transfers the data read to the opposite direction read data queue, pointing toward the opposite in ter-face, before terminating the
PI7C7300D 3-port pci-to-pci bridge page 31 of 107 pericom semiconductor november 2005 - revision 1.01 transaction. for example, read data in response to a downstream read transaction initiated on the primary bus is placed in the upstream read da ta queue. the PI7C7300D can accept one dword of read data each pci clock cycle; that is, no mast er wait states are inserted. the number of dword transferred during a delayed read transactio n depends on the conditions given in
PI7C7300D 3-port pci-to-pci bridge page 32 of 107 pericom semiconductor november 2005 - revision 1.01 table 4-5 (assuming no disconnect is received from the target). 4.7.6 delayed read completion on initiator bus when the transaction has been completed on th e target bus, and the delayed read data is at the head of the read data queue, and all ordering constraints with posted write transactions have been satisfied, the PI7C7300D transfers the data to the initiator when the initiator repeats th e transaction. for memory read transactions, PI7C7300D aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction to the bus command in the delayed transaction queue. PI7C7300D returns a target disconnect along with the transfer of the last dword of read data to the initia tor. if PI7C7300D initiator terminates the transaction before all read data has been transferred, the remaining read data left in data buffers is discarded. when the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read transaction starts operating in flow-through mode. because da ta is flowing through the data buffers from the target to the initiator, long read bursts can then be sustained. in this case, the read transaction is allowed to continue until the initiator terminates the trans-action, or until an aligned 4kb address boundary is reached, or until the buffe r fills, whichever comes first. when the buffer empties, PI7C7300D reflects the stalle d condition to the initiator by disconnecting the initiator with data. the initiator may retry the transaction later if data are needed. if the initiator does not need any more data, the initiator will not continue the disconnected transaction. in this case, PI7C7300D will st art the master timeout timer. the remaining read data will be discarded after the master timeout timer expires. to provide better latency, if there are any other pending data for other transactions in the rdb (read data buffer), the remaining read data will be di scarded even though the master timeout timer has not expired. PI7C7300D implements a master timeout timer that starts counting when the delayed read completion is at the head of the delayed transaction queue, and the read data is at the head of the read data queue. the initial va lue of this timer is program-mable through configuration register. if the initiator does not repeat the read transaction and before the master timeout timer expires (2 15 default), PI7C7300D discards the read transaction and read data from its queues. PI7C7300D also conditionally asserts p_serr# (see section 7.4 ). PI7C7300D has the capability to post multiple delayed read requests, up to a maximum of four in each direction. if an initiator starts a read trans action that matches the address and read command of a read transaction th at is already queued, the current read command is not posted as it is already contained in the delayed transaction queue. see section 6 for a discussion of how delayed read transactions are ordered when crossing PI7C7300D. 4.7.7 fast back-to-back read transaction
PI7C7300D 3-port pci-to-pci bridge page 33 of 107 pericom semiconductor november 2005 - revision 1.01 PI7C7300D can recognize fast back-to-back read transactions. 4.8 configuration transactions configuration transactions are used to initialize a pci system. every pci device has a configuration space that is accessed by configuration commands. all registers are accessible in configuration space only. in addition to accepting configuration tran sactions for initialization of its own configuration space, the PI7C7300D also forwards configuration tran sactions for device initialization in hierarchical pci systems, as well as for special cycle generation. to support hierarchical pci bus systems, two types of configuration transactions are specified: type 0 and type 1. type 0 configuration transactions are issued when the intended target resides on the same pci bus as the initiator. a type 0 configuration transaction is identified by the configuration command and the lowest two bits of the address set to 00b. type 1 configuration transactions are issued when the intended target resides on another pci bus, or when a special cycle is to be generated on another pci bus. a type 1 configuration command is identified by the configuration command and the lowest two address bits set to 01b. the register number is found in both type 0 and type 1 formats and gives the dword address of the configuration re gister to be accessed. the f unction number is also included in both type 0 and type 1 formats and indicates which function of a multifunction device is to be accessed. for single-function devices, this value is not decoded. the addresses of type 1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target pc i bus that is to be accessed. in addition, the bus number in type 1 transactions specifies the pci bus to which the transaction is targeted. 4.8.1 type 0 access to PI7C7300D the configuration space is accessed by a type 0 configuration transaction on the primary interface. the configuration space cannot be accessed from the secondary bus. the PI7C7300D responds to a type 0 configura tion transaction by asserting p_devsel# when the following conditions are met during the address phase: the bus command is a configuration read or configuration write transaction. lowest two address bits p_ad[1:0] must be 00b. signal p_idsel must be asserted. function code is either 0 for configuration space of s1, or 1 for configuration space of s2 as PI7C7300D is a multi-function device. PI7C7300D limits all configuration access to a single dword data transfer and returns target-disconnect with the first data transfer if additional data phases are requested.
PI7C7300D 3-port pci-to-pci bridge page 34 of 107 pericom semiconductor november 2005 - revision 1.01 because read transactions to configuration sp ace do not have side effects, all bytes in the requested dword are returned, regardless of the value of the byte enable bits. type 0 configuration write and read transac tions do not use data buffers; that is, these transactions are completed immediately, rega rdless of the state of the data buffers. the PI7C7300D ignores all type 0 transacti ons initiated on the secondary interface. 4.8.2 type 1 to type 0 conversion type 1 configuration transactions are used specifically for device configuration in a hierarchical pci bus system. a pci-to-pci bridge is the only type of device that should respond to a type 1 configuration command. type 1 configuration commands are used when the configuration access is intended fo r a pci device that resides on a pci bus other than the one where the type 1 transaction is generated. PI7C7300D performs a type 1 to type 0 translation when the type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. PI7C7300D must convert the configuration command to a type 0 format so that the secondary bus device can respond to it. type 1 to type 0 translations are performed only in the downstream direction; that is, PI7C7300D generates a type 0 transaction only on the secondary bus, and never on the primary bus. PI7C7300D responds to a type 1 configuration tr ansaction and translates it into a type 0 transaction on the secondary bus when th e following conditions are met during the address phase: the lowest two address bits on p_ad[1:0] are 01b. the bus number in address field p_ad[23:16] is equal to the value in the secondary bus number register in configuration space. the bus command on p_cbe[3:0] is a configuration read or configuration write transaction. when PI7C7300D translates the type 1 transaction to a type 0 transaction on the secondary interface, it performs the follo wing translations to the address: sets the lowest two address bits on s1_ad[1:0] or s2_ad[1:0] to 00b. decodes the device number and drives the bit pattern specified in table 4-6 on s1_ad[31:16] or s2_ad[31:16] for the purpose of asserting the device?s idsel signal. sets s1_ad[15:11] or s2_ad[15:11] to 0. leaves unchanged the function numbe r and register number fields. PI7C7300D asserts a unique address line ba sed on the device number. these address lines may be used as secondary bus idsel signals. the mapping of the address lines depends on the device number in the type 1 address bits p_ad[15:11]. table 4-6 presents the mapping that PI7C7300D uses. table 4-6 device number to idsel s1_ad or s2_ad pin mapping device number p_ad[15:11] secondary idsel s1_ad[31:16] or s2_ad[31:16] s1_ad or s2_ad
PI7C7300D 3-port pci-to-pci bridge page 35 of 107 pericom semiconductor november 2005 - revision 1.01 0h 00000 0000 0000 0000 0001 16 1h 00001 0000 0000 0000 0010 17 2h 00010 0000 0000 0000 0100 18 3h 00011 0000 0000 0000 1000 19 4h 00100 0000 0000 0001 0000 20 5h 00101 0000 0000 0010 0000 21 6h 00110 0000 0000 0100 0000 22 7h 00111 0000 0000 1000 0000 23 8h 01000 0000 0001 0000 0000 24 9h 01001 0000 0010 0000 0000 25 ah 01010 0000 0100 0000 0000 26 bh 01011 0000 1000 0000 0000 27 ch 01100 0001 0000 0000 0000 28 dh 01101 0010 0000 0000 0000 29 eh 01110 0100 0000 0000 0000 30 fh 01111 1000 0000 0000 0000 31 10h ? 1eh 10000 ? 11110 0000 0000 0000 0000 - 1fh 11111 generate special cycle (p_ad[7:2] = 00h) 0000 0000 0000 0000 (p_ad[7:2] = 00h) - PI7C7300D can assert up to 16 unique address lin es to be used as idsel signals for up to 16 devices on the secondary bus, for device numbers ranging from 0 through 15. because of electrical loading constraints of the pci bus, more than 16 idsel signals should not be necessary . however, if device numbers greater than 15 are desired, some external method of generating idsel lines mu st be used, and no upper address bits are then asserted. the configuration transaction is still translated and passed from the primary bus to the secondary bus. if no idsel pin is asserted to a secondary device, the transaction ends in a master abort. PI7C7300D forwards type 1 to type 0 configuration read or write transactions as delayed transactions. type 1 to type 0 configuration read or write transactions are limited to a single 32-bit data transfer. 4.8.3 type 1 to type 1 forwarding type 1 to type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of pci-to-pci bridges are used. when PI7C7300D detects a type 1 configuration transaction intended for a pci bus downstream from the secondary bus, PI7C7300D forwards the transaction unchanged to the secondary bus. ultimately, this transacti on is translated to a type 0 configuration command or to a special cycle transac tion by a downstream pci-to-pci bridge. downstream type 1 to type 1 forwarding occurs when the following conditions are met during the address phase: the lowest two address bits are equal to 01b. the bus number falls in the range define d by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. the bus command is a configuration read or write transaction.
PI7C7300D 3-port pci-to-pci bridge page 36 of 107 pericom semiconductor november 2005 - revision 1.01 PI7C7300D also supports type 1 to type 1 forwarding of configuration write transactions upstream to support upstream special cycle generation. a type 1 configuration command is forwarded upstream when the following conditions are met: the lowest two address bits are equal to 01b. the bus number falls outside the range de fined by the lower limit (inclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. the device number in address bits ad[15:11] is equal to 11111b. the function number in address bits ad[10:8] is equal to 111b. the bus command is a configuration write transaction. the PI7C7300D forwards type 1 to type 1 configuration write transactions as delayed transactions. type 1 to type 1 configuration write transactions are limited to a single data transfer. 4.8.4 special cycles the type 1 configuration mechanism is used to generate special cycle transactions in hierarchical pci systems. special cycle transactions are ignored by acting as a target and are not forwarded across the bridge. special cycle transactions can be generated from type 1 configuration write transactions in either the upstream or the down-stream direction. PI7C7300D initiates a special cycle on the target bus when a type 1 configuration write transaction is being detected on the initia ting bus and the following conditions are met during the address phase: the lowest two address bits on ad[1:0] are equal to 01b. the device number in address bits ad[15:11] is equal to 11111b. the function number in address bits ad[10:8] is equal to 111b. the register number in address bits ad[7:2] is equal to 000000b. the bus number is equal to the value in the secondary bus number register in configuration space for downstream forwarding or equal to the va lue in the primary bus number register in configura tion space for upstream forwarding. the bus command on cbe# is a configuration write command. when PI7C7300D initiates the transaction on the target interface, the bus command is changed from configuration write to special cycle. the address and data are for-warded unchanged. devices that use special cycles ignore the address and decode only the bus command. the data phase contains the sp ecial cycle message. the transaction is forwarded as a delayed transaction, but in this case the target response is not forwarded back (because special cycles re sult in a master abort). once the transaction is completed on the target bus, through detection of the master abort condition, PI7C7300D responds with trdy# to the next attempt of the con-figuration transaction from the initiator. if more than one data transfer is requested, PI7C7300D responds with a target disconnect operation during the first data phase.
PI7C7300D 3-port pci-to-pci bridge page 37 of 107 pericom semiconductor november 2005 - revision 1.01 4.9 transaction termination this section describes how PI7C7300D returns transaction termination conditions back to the initiator. the initiator can terminate transactions with one of the following types of termination: normal termination normal termination occurs when the initiator de-asserts frame# at the beginning of the last data phase, and de-asserts irdy# at the end of the last data phase in conjunction with either trdy# or stop# assertion from the target. master abort a master abort occurs when no target re sponse is detected. when the initiator does not detect a devsel# from the target with in five clock cycl es after asserting frame#, the initiator terminates the transaction with a master abort. if frame# is still asserted, the initiator de-asserts frame# on the next cycle, and then de-asserts irdy# on the following cycle. irdy# must be asserted in the same cycle in which frame# de-asserts. if frame# is alread y de-asserted, irdy# can be de-asserted on the next clock cycle following detection of the master abort condition. the target can terminate transactions with one of the following types of termination: normal termination trdy# and devsel# asserted in conj unction with frame# de-asserted and irdy# asserted. target retry stop# and devsel# asserted with trdy# de-asserted during the first data phase. no data transfers occur during the transac tion. this transaction must be repeated. target disconnect with data transfer stop#, devsel# and trdy# asserted. it signals that this is the last data transfer of the transaction. target disconnect without data transfer stop# and devsel# asserted with trdy# de-asserted after previous data transfers have been made. indicates that no more data transfers will be made during this transaction. target abort stop# asserted with devsel# and trdy# de-asserted. indicates that target will never be able to complete this transaction. devsel# must be asserted for at least one cycle during the transaction before the target abort is signaled. 4.9.1 master termination initiated by PI7C7300D PI7C7300D, as an initiator, uses normal termination if devsel# is returned by target within five clock cycles of PI7C7300D?s assertion of frame# on the target bus. as an initiator, PI7C7300D terminates a transac tion when the following conditions are met: during a delayed write transaction, a single dword is delivered. during a non-prefetchable read transaction, a single dword is transferred from the target. during a prefetchable read transac tion, a pre-fetch boundary is reached.
PI7C7300D 3-port pci-to-pci bridge page 38 of 107 pericom semiconductor november 2005 - revision 1.01 for a posted write transaction, all write data for the transaction is transferred from data buffers to the target. for burst transfer, with the exception of ?memory write and invalidate? transactions, the master latency timer expires and the PI7C7300D?s bus grant is de- asserted. the target terminates the transaction with a retry, disconnect, or target abort. if PI7C7300D is delivering posted write data wh en it terminates the transaction because the master latency timer expires, it initiates another transaction to deliver the remaining write data. the address of the transaction is updated to reflect the address of the current dword to be delivered. if PI7C7300D is pre-fetching read data when it terminates the tran saction because the master latency timer expires, it does not repeat the transaction to obtain more data. 4.9.2 master abort received by PI7C7300D if the initiator initiates a transaction on the target bus and does not detect devsel# returned by the target within five clock cycles of the assertion of frame#, PI7C7300D terminates the transaction with a master abor t. this sets the received-master-abort bit in the status register corresponding to the target bus. for delayed read and write transactions, PI7C7300D is able to reflect the master abort condition back to the initiator. when PI7C7300D detects a master abort in response to a delayed transaction, and when the initiator repeats the transaction, PI7C7300D does not respond to the transaction with devsel# which induces the master abort condition back to the initiator. the transaction is then removed from the delayed transaction queue. when a master abort is received in respons e to a posted write transaction, PI7C7300D discards the posted write data and makes no more attempts to deliver the data. PI7C7300D sets the received-master-abort bit in the status register when the master abort is received on the primary bus, or it sets the received master abort bit in the secondary status register when the master abort is r eceived on the secondary interface. when master abort is detected in posted write transaction with both master-abort-mode bit (bit 5 of bridge control register) and the serr# enable bit (bit 8 of command register for secondary bus s1 or s2) are set, PI7C7300D asserts p_serr# if the master-abort-on- posted-write is not set. the master-abort-on-posted-write bit is bit 4 of the p_serr# event disable register (offset 64h). note: when PI7C7300D performs a type 1 to special cycle conversion, a master abort is the expected termination for the special cycle on the target bus. in this case, the master abort received bit is not set, and the type 1 configuration trans action is disconnected after the first data phase. 4.9.3 target termination received by PI7C7300D when PI7C7300D initiates a transaction on the target bus and the target responds with devsel#, the target can end the transaction with one of the following types of termination:
PI7C7300D 3-port pci-to-pci bridge page 39 of 107 pericom semiconductor november 2005 - revision 1.01 normal termination (upon de-assertion of frame#) target retry target disconnect target abort PI7C7300D handles these terminations in different ways, depending on the type of transaction being performed. 4.9.3.1 delayed write target termination response when PI7C7300D initiates a delayed write trans action, the type of target termination received from the target can be passed back to the initiator. table 4-7 shows the response to each type of target termination that occurs during a delayed write transaction. PI7C7300D repeats a delayed write transacti on until one of the following conditions is met: PI7C7300D completes at least one data transfer. PI7C7300D receives a master abort. PI7C7300D receives a target abort. PI7C7300D makes 2 24 (default) or 2 32 (maximum) write attempts resulting in a response of target retry. table 4-7 delayed write target termination response target termination response normal returning disconnect to initiator with first data tr ansfer only if multiple data phases requested. target retry returning target retry to initiator. continue write attempts to target target disconnect returning disconn ect to initiator with first data transfer only if multiple data phases requested. target abort returning target abor t to initiator. set received targ et abort bit in target interface status register. set signaled target abor t bit in initiator interface status register. after the PI7C7300D makes 2 24 (default) attempts of the same delayed write trans-action on the target bus, PI7C7300D asserts p_serr# if the serr# enable bit (bit 8 of command register for secondary bus s1 or s2) is set and the delayed-write-non- delivery bit is not set. the delayed-write-non-delivery bit is bit 5 of p_serr# event disable register (offset 64h). PI7C7300D will report system error. see section 7.4 for a description of system error conditions. 4.9.3.2 posted write target termination response when PI7C7300D initiates a posted write trans action, the target termination cannot be passed back to the initiator. table 4-8 shows the response to each type of target termination that occurs during a posted write transaction. table 4-8 response to posted write target termination target termination repsonse normal no additional action. target retry repeating write transaction to target. target disconnect initiate write transaction for delivering remaining posted write data.
PI7C7300D 3-port pci-to-pci bridge page 40 of 107 pericom semiconductor november 2005 - revision 1.01 target termination repsonse target abort set received-target-abort bit in th e target interface status register. assert p_serr# if enabled, and set the signale d-system-error bit in primary status register. note that when a target retry or target disconnect is returned and posted write data associated with that trans action remains in the write bu ffers, PI7C7300D initiates another write transaction to attempt to deliver the rest of the write data. if there is a target retry, the exact same address will be driven as for the initial write trans-action attempt. if a target disconnect is received, the address that is driven on a subsequent write transaction attempt will be updated to reflect the addre ss of the current dword. if the initial write transaction is memory-write-and-invalidate tr ansaction, and a partial delivery of write data to the target is performed before a target disconnect is received, PI7C7300D will use the memory write command to deliver the rest of the write data. it is because an incomplete cache line will be tr ansferred in the subsequent write transaction attempt. after the PI7C7300D makes 2 24 (default) write transaction attempts and fails to deliver all posted write data associated with that transaction, PI7C7300D asserts p_serr# if the primary serr# enable bit is set (bit 8 of command register for secondary bus s1 or s2) and posted-write-non-delivery bit is not set. the posted-write-non-delivery bit is the bit 2 of p_serr# event disable register (offset 64h). PI7C7300D will report system error. see section 7.4 for a discussion of system error conditions. 4.9.3.3 delayed read targ et termination response when PI7C7300D initiates a delayed read trans action, the abnormal target responses can be passed back to the initiator. other targ et responses depend on how much data the initiator requests. table 4-9 shows the response to each type of target termination that occurs during a delayed read transaction. PI7C7300D repeats a delayed read transacti on until one of the following conditions is met: PI7C7300D completes at least one data transfer. PI7C7300D receives a master abort. PI7C7300D receives a target abort. PI7C7300D makes 2 24 (default) read attempts resulting in a response of target retry. table 4-9 response to delayed read target termination target termination response normal if prefetchable , target disconnect only if initiato r requests more data than read from target. if non-prefetchable, ta rget disconnect on first data phase. target retry re-initiate r ead transaction to target target disconnect if initiator request s more data than read from targ et, return target disconnect to initiator. target abort return target abor t to initiator. set received ta rget abort bit in the target interface status register. set signaled ta rget abort bit in the initiator interface status register. after PI7C7300D makes 2 24 (default) attempts of the same delayed read transaction on the target bus, PI7C7300D asserts p_serr# if the primary serr# enable bit is set (bit 8 of command register for secondary bus s1 or s2) and the delayed-write-non-delivery bit is not set. the delayed-write-non-delivery bit is bit 5 of p_serr# event disable register
PI7C7300D 3-port pci-to-pci bridge page 41 of 107 pericom semiconductor november 2005 - revision 1.01 (offset 64h). PI7C7300D will report system error. see section 7.4 for a description of system error conditions. 4.9.4 target termination initiated by PI7C7300D PI7C7300D can return a target retry, target di sconnect, or target abort to an initiator for reasons other than detection of that condition at the target interface. 4.9.4.1 target retry PI7C7300D returns a target retry to the in itiator when it cannot accept write data or return read data as a result of internal conditions. PI7C7300D returns a target retry to an initiator when any of the following conditions is met: for delayed write transactions: the transaction is being entered into the delayed transaction queue. transaction has already been entered into delayed transaction queue, but target response has not yet been received. target response has been recei ved but has not progressed to the head of the return queue. the delayed transaction queue is full, and the transaction cannot be queued. a transaction with the same address and command has been queued. a locked sequence is being propagated across PI7C7300D, and the write transaction is not a locked transaction. the target bus is locked and the write transaction is a locked transaction. use more than 16 clocks to accept this transaction. for delayed read transactions: the transaction is being entered into the delayed transaction queue. the read request has already been queued, but read data is not yet available. data has been read from target, but it is not yet at head of the read data queue or a posted write transaction precedes it. the delayed transaction queue is full, and the transaction cannot be queued. a delayed read request with the same address and bus command has already been queued. a locked sequence is being propagated across PI7C7300D, and the read transaction is not a locked transaction. PI7C7300D is currently discarding previously pre-fetched read data. the target bus is locked and the write transaction is a locked transaction. use more than 16 clocks to accept this transaction. for posted write transactions: the posted write data buffer does not have enough space for address and at least one dword of write data. a locked sequence is being propagated across PI7C7300D, and the write transaction is not a locked transaction.
PI7C7300D 3-port pci-to-pci bridge page 42 of 107 pericom semiconductor november 2005 - revision 1.01 when a target retry is returned to the initiator of a delayed transaction, the initiator must repeat the transaction with the same address and bus command as well as the data if it is a write transaction, within the time frame specified by the master timeout value. otherwise, the transaction is discarded from the buffers. 4.9.4.2 target disconnect PI7C7300D returns a target disconnect to an initiator when one of the following conditions is met: PI7C7300D hits an internal address boundary. PI7C7300D cannot accept any more write data. PI7C7300D has no more read data to deliver. see section 4.6.4 for a description of write address boundaries, and section 4.7.3 for a description of read address boundaries. 4.9.4.3 target abort PI7C7300D returns a target abort to an initiator when one of the following conditions is met: PI7C7300D is returning a target abort from the intended target. when PI7C7300D returns a target abort to the initiator, it sets the signaled target abort bit in the status register corre sponding to the initiator interface. 4.10 concurrent mode operation the bridge can be configured to run in c oncurrent operation. c oncurrent operation is defined as cycles going from one device on one secondary bus to another device on the same or other secondary bus. this off-loads traffic from the primary bus, allowing other traffic to run on the primary bus concurrently. the bridge is already configured to handle concurrent operation. however, the devices themselves need to be configured to do so. meaning, device drivers for the specific device used will have to be configured to perform the operation. please see section 5.1 for more information on addressing. 5 address decoding PI7C7300D uses three address ranges that control i/o and memory transaction forwarding. these address ranges are defined by base and limit address registers in the configuration space. this chapter describes these address ranges, as well as isa-mode and vga-addressing support.
PI7C7300D 3-port pci-to-pci bridge page 43 of 107 pericom semiconductor november 2005 - revision 1.01 5.1 address ranges PI7C7300D uses the following address ranges that determine which i/o and memory transactions are forwarded from the primary pci bus to the secondary pci bus, and from the secondary bus to the primary bus: two 32-bit i/o address ranges two 32-bit memory-mapped i/o (non-prefetchable memory) ranges two 32-bit prefetchable memory address ranges transactions falling within these ranges ar e forwarded downstream from the primary pci bus to the two secondary pci buses. tran sactions falling outside these ranges are forwarded upstream from the two secondary pci buses to the primary pci bus. no address translation is required in PI7C7300D. the addresses that are not marked for downstream are always forwarded upstream. ho wever, if an address of a transaction initiated from s1 bus is located in the marked address range for down-stream in s2 bus and not in the marked address range for downstream in s1 bus, the transaction will be forwarded to s2 bus instead of primary bus. by the same token, if an address of a transaction initiated from s2 bus is located in the marked address range for downstream in s1 bus and not in the marked address range for downstream in s2 bus, the transaction will be forwarded to s1 bus instead of primary bus. 5.2 i/o address decoding PI7C7300D uses the following mechanisms that are defined in the configuration space to specify the i/o address space for dow nstream and upstream forwarding: i/o base and limit address registers the isa enable bit the vga mode bit the vga snoop bit this section provides information on the i/o address registers and isa mode. section 5.4 provides information on the vga modes. to enable downstream forwarding of i/o trans actions, the i/o enable bit must be set in the command register in configuration space. all i/o transactions initiated on the primary bus will be ignored if the i/o enable bit is not set. to enable upstream forwarding of i/o transactions, the master enable bit must be set in the command register. if the master- enable bit is not set, PI7C7300D ignores all i/o and memory transactions initiated on the secondary bus. the master-enable bit also allows upstream forwarding of memory transactions if it is set. caution if any configuration state affecting i/o transaction forwarding is changed by a configuration write operation on the primary bus at the same time that i/o
PI7C7300D 3-port pci-to-pci bridge page 44 of 107 pericom semiconductor november 2005 - revision 1.01 transactions are ongoing on the secondary bus, PI7C7300D response to the secondary bus i/o transactions is not predictable. configure the i/o base and limit address registers, isa enable bit, vga mode bit, and vga snoop bit before setting i/o enable and master enable bits, and change them subsequently only when the primary and secondary pci buses are idle. 5.2.1 i/o base and limit address register PI7C7300D implements one set of i/o base and limit address registers in configuration space that define an i/o address range per port downstream forwarding. PI7C7300D supports 32-bit i/o addressing, which allo ws i/o addresses downstream of PI7C7300D to be mapped anywhere in a 4gb i/o address space. i/o transactions with addresses that fall insi de the range defined by the i/o base and limit registers are forwarded downstream from the primary pci bus to the secondary pci bus. i/o transactions with addresses that fall out side this range are forwarded upstream from the secondary pci bus to the primary pci bus. the i/o range can be turned off by setting th e i/o base address to a value greater than that of the i/o limit address. when the i/o range is turned off, all i/o trans-actions are forwarded upstream, and no i/o transactions are forwarded downstream. the i/o range has a minimum granularity of 4kb and is aligned on a 4kb boundary. the maximum i/o range is 4gb in size. the i/o base register consists of an 8-bit field at configuration address 1ch, and a 16-bit field at address 30h. the top 4 bits of the 8-bit field define bits [15:12] of the i/o base address. the bottom 4 bits read only as 1h to indicate that PI7C7300D supports 32-bit i/o addressing. bits [11:0] of the base address are assumed to be 0, which naturally aligns the base address to a 4kb boundary. the 16 bits contained in the i/o base upper 16 bits register at configuration offset 30h define ad[ 31:16] of the i/o base address. all 16 bits are read/write. after primary bus reset or chip reset, the value of the i/o base address is initialized to 0000 0000h. the i/o limit register consists of an 8-bit field at configuration offset 1dh and a 16-bit field at offset 32h. the top 4 bits of the 8-bit field define bits [15:12] of the i/o limit address. the bottom 4 bits read only as 1h to indicate that 32-bit i/o addressing is supported. bits [11:0] of the limit address ar e assumed to be fffh, which naturally aligns the limit address to the top of a 4kb i/o address block. the 16 bits contained in the i/o limit upper 16 bits register at configuration offset 32h define ad[31:16] of the i/o limit address. all 16 bits are read/write. after primar y bus reset or chip reset, the value of the i/o limit address is reset to 0000 0fffh. note: the initial states of the i/o base and i/o limit address registers define an i/o range of 0000 0000h to 0000 0fffh, which is the bottom 4kb of i/o space. write these registers with their appropriate values before setting either the i/o enable bit or the master enable bit in the command register in configuration space.
PI7C7300D 3-port pci-to-pci bridge page 45 of 107 pericom semiconductor november 2005 - revision 1.01 5.2.2 isa mode PI7C7300D supports isa mode by providing an isa enable bit in the bridge control register in configuration space. isa mode modifies the response of PI7C7300D inside the i/o address range in order to support mapping of i/o space in the presence of an isa bus in the system. this bit only affects the response of PI7C7300D when the transaction falls inside the address range defined by the i/o base and limit address registers, and only when this address also falls inside the fi rst 64kb of i/o space (address bits [31:16] are 0000h). when the isa enable bit is set, PI7C7300D does not forward downstream any i/o transactions addressing the top 768 bytes of each ali gned 1kb block. only those transactions addressing the bottom 256 bytes of an aligned 1kb block inside the base and limit i/o address range are forwarded dow nstream. transactions above the 64kb i/o address boundary are forwarded as defined by the address range defined by the i/o base and limit registers. accordingly, if the isa enable bit is set, PI7C7300D forwards upstream those i/o transactions addressing the top 768 bytes of each aligned 1kb block within the first 64kb of i/o space. the master enable bit in the command configura tion register must also be set to enable upstream forwarding. all other i/o transactions initiated on the secondary bus are forwarded upstream only if they fall outside the i/o address range. when the isa enable bit is set, devices downstream of PI7C7300D can have i/o space mapped into the first 256 bytes of each 1kb chunk below the 64kb boundary, or anywhere in i/o space above the 64kb boundary. 5.3 memory address decoding PI7C7300D has three mechanisms for defining memory address ranges for forwarding of memory transactions: memory-mapped i/o base and limit address registers prefetchable memory base and limit address registers vga mode this section describes the first two mechanisms. section 5.4.1 describes vga mode. to enable downstream forwarding of memory tran sactions, the memory enable bit must be set in the command register in configurati on space. to enable upstream forwarding of memory transactions, the master-enable bit must be set in the command register. the master-enable bit also allows upstream forwarding of i/o transactions if it is set. caution if any configuration state affecting memory transaction forwarding is changed by a configuration write operation on the primary bus at the same time that memory transactions are ongoing on the secondary bus, response to the secondary bus memory transactions is not predictable. configure the memory-mapped i/o base and limit address registers, prefetchable memory base and limit address registers, and vga mode bit before setting the memory enable and master enable bits, and change them subsequently only when the primary and secondary pci buses are idle.
PI7C7300D 3-port pci-to-pci bridge page 46 of 107 pericom semiconductor november 2005 - revision 1.01 5.3.1 memory-mapped i/o base and limit address registers memory-mapped i/o is also referred to as non-prefetchable memory. memory addresses that cannot automatically be pre-fetched but that can be conditionally prefetched based on command type should be mapped into th is space. read trans-actions to non- prefetchable space may exhibit side effects; this space may have non-memory-like behavior. PI7C7300D prefetches in this space only if the memory read line or memory read multiple commands are used; transactions using the memory read command are limited to a single data transfer. the memory-mapped i/o base address and memory-mapped i/o limit address registers define an address range that PI7C7300D uses to determine when to forward memory commands. PI7C7300D forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the memory-mapped i/o address range. PI7C7300D ignor es memory transactions initiated on the secondary interface that fall into this a ddress range. any transactions th at fall outside this address range are ignored on the primary interf ace and are forwarded upstream from the secondary interface (provided that they do not fall into the prefetchable memory range or are not forwarded downstream by the vga mechanism). the memory-mapped i/o range supports 32-bit addressing only. the pci-to-pci bridge architecture specification does not provide for 64-bit addressing in the memory-mapped i/o space. the memory-mapped i/o address ra nge has a granularity and alignment of 1mb. the maximum memory-mapped i/o address range is 4gb. the memory-mapped i/o address range is de fined by a 16-bit memory-mapped i/o base address register at configuration offset 20h and by a 16-bit memory-mapped i/o limit address register at offset 22h. the top 12 bits of each of these registers correspond to bits [31:20] of the memory address. the low 4 bits are hardwired to 0. the lowest 20 bits of the memory-mapped i/o base address are assumed to be 0 0000h, which results in a natural alignment to a 1mb boundary. the lowest 20 bits of the memory-mapped i/o limit address are assumed to be fffffh, which re sults in an alignment to the top of a 1mb block. note: the initial state of the memory-mapped i/o base address re gister is 0000 0000h. the initial state of the memory-mapped i/o limit address register is 000f ffffh. note that the initial stat es of these registers define a memory-mapped i/o range at the bottom 1mb block of memory. write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. to turn off the memory-mapped i/o addre ss range, write the memory-mapped i/o base address register with a value greater than that of the memory-mapped i/o limit address register.
PI7C7300D 3-port pci-to-pci bridge page 47 of 107 pericom semiconductor november 2005 - revision 1.01 5.3.2 prefetchable memory base and limit address registers locations accessed in the prefetchable memory address range must have true memory- like behavior and must not exhibit side effect s when read. this mean s that extra reads to a prefetchable memory location must have no side effects. PI7C7300D pre-fetches for all types of memory read commands in this address space. the prefetchable memory base address and prefetchable memory limit address registers define an address range that PI7C7300D uses to determine when to for- ward memory commands. PI7C7300D forwards a memory transaction from the primary to the secondary interface if the transaction addre ss falls within the pr efetchable memory address range. PI7C7300D ignor es memory transactions initiated on the secondary interface that fall into this address range. PI7C7300D does not respond to any transactions that fall outside this addre ss range on the primary interface and forwards those transactions upstream from the secondary interface (provided that they do not fall into the memory-mapped i/o range or are not forwarded by the vga mechanism). the prefetchable memory range supports 64-bit addressing and provides additional registers to define the upper 32 bits of the memory address range, the prefetchable memory base address upper 32 bits register, and the prefetchable memory limit address upper 32 bits register. for address comparison, a single address cycle (32-bit address) prefetchable memory transaction is treated like a 64-bit address transaction where the upper 32 bits of the address are equal to 0. this upper 32-bit value of 0 is compared to the prefetchable memory base address upper 32 bits register and the prefetchable memory limit address upper 32 bits register. the prefetchable memory base address upper 32 bits register must be 0 to pass any single address cycle transactions downstream. prefetchable memory address range has a granularity and alignment of 1mb. maximum memory address range is 4gb when 32-bit addressing is being used. prefetchable memory address range is defined by a 16-bit prefetchable memory base address register at configuration offset 24h and by a 16-bit prefetchable memory limit address register at offset 26h. the top 12 bits of each of these registers correspond to bits [31:20] of the memory address. the lowest 4 bits are hardwired to 1h. the lowest 20 bits of the prefetchable memory base address are assumed to be 0 0000h, which results in a natural alignment to a 1mb boundary. the lowest 20 bits of the prefetchable memory limit address are assumed to be fffffh, which results in an alignment to the top of a 1mb block. note: the initial state of the pref etchable memory base a ddress register is 0000 0000h. the initial state of the prefet chable memory limit address register is 000f ffffh. note that the initial states of these registers define a prefetchable memory range at the bottom 1mb block of memory. write these registers with their appropriate values before setting either the memory enable bit or the mast er enable bit in th e command register in configuration space. to turn off the prefetchable memory addre ss range, write the prefetchable memory base address register with a value greater than th at of the prefetchable memory limit address register. the entire base value must be great er than the entire limit value, meaning that the upper 32 bits must be considered. therefore, to disable the address range, the upper
PI7C7300D 3-port pci-to-pci bridge page 48 of 107 pericom semiconductor november 2005 - revision 1.01 32 bits registers can both be set to the same value, while the lower base register is set greater than the lower limit register. otherwise, the upper 32-bit base must be greater than the upper 32-bit limit. 5.4 vga support PI7C7300D provides two modes for vga support: vga mode, supporting vga-compatible addressing vga snoop mode, supporting vga palette forwarding 5.4.1 vga mode when a vga-compatible device exists downstream from PI7C7300D, set the vga mode bit in the bridge control register in configuration space to enable vga mode. when PI7C7300D is operating in vga mode, it forwards downstream those transactions addressing the vga frame buffer memory a nd vga i/o registers, regardless of the values of the base and limit address regist ers. PI7C7300D ignores transactions initiated on the secondary interface addressing these locations. the vga frame buffer consists of the following memory address range: 000a 0000h?000b ffffh read transactions to frame buffer memory are treated as non-prefetchable. PI7C7300D requests only a single data transfer from the target, and read byte enable bits are forwarded to the target bus. the vga i/o addresses are in the range of 3b0h?3bbh and 3c0h?3dfh i/o. these i/o addresses are aliases every 1kb throughout the first 64kb of i/o space. this means that address bits <15:10> are not decoded and can be any value, while address bits [31:16] must be all 0s. vga bios addresses star ting at c0000h are not decoded in vga mode. 5.4.2 vga snoop mode PI7C7300D provides vga snoop mode, allowing fo r vga palette write transactions to be forwarded downstream. this mode is used when a graphics device downstream from PI7C7300D needs to snoop or respond to vga palette write transactions. to enable the mode, set the vga snoop bit in the command regi ster in configuration space. note that PI7C7300D claims vga palette write transactions by asserting devsel# in vga snoop mode. when vga snoop bit is set, PI7C7300D forwards downstream transactions within the 3c6h, 3c8h and 3c9h i/o addresses space. note that thes e addresses are also forwarded as part of the vga compatibility mode prev iously described. ag ain, address bits <15:10> are not decoded, while address bits <31:16> must be equal to 0, which means that these addresses are aliases every 1kb throughout the first 64kb of i/o space.
PI7C7300D 3-port pci-to-pci bridge page 49 of 107 pericom semiconductor november 2005 - revision 1.01 note: if both the vga mode bit and the vga snoop bit are set, PI7C7300D behaves in the same way as if only the vga mode bit were set. 6 transaction ordering to maintain data coherency and consiste ncy, PI7C7300D complies with the ordering rules set forth in the pci local bus specification , revision 2.2 , for transactions crossing the bridge. this chapter describes the ordering rules that control transaction forwarding across PI7C7300D. 6.1 transactions governed by ordering rules ordering relationships are established for the following classes of transactions crossing PI7C7300D: posted write transactions, comprised of memory write a nd memory write and invalidate transactions. posted write transactions complete at the source before they complete at the destination; that is, data is written into intermediate data buffers before it reaches the target. delayed write request transactions, compri sed of i/o write and configuration write transactions. delayed write requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. a delayed write transaction must complete on the target bus before it completes on the initiator bus. delayed write completion transactions, comprised of i/o write and configuration write transactions. delayed write completion transactions complete on the target bus, and the target response is queued in the buffers. a delayed write comp letion transaction proceeds in the direction opposite that of the original delayed write request; that is, a delayed write completion transaction proceeds from the target bus to the initiator bus. delayed read request transactions, compri sed of all memory read, i/o read, and configuration read transactions. delayed read requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. delayed read completion transactions, comprised of all memory read, i/o read, & configuration read transactions. delayed read completion transactions complete on the target bus, and the read data is queued in the read data buffers. a delayed read completion transaction proceeds in the direction opposite that of the original delayed read request; that is, a delayed read completion transaction proceeds from th e target bus to the initiator bus. PI7C7300D does not combine or merge write transactions:
PI7C7300D 3-port pci-to-pci bridge page 50 of 107 pericom semiconductor november 2005 - revision 1.01 PI7C7300D does not combine separate write transactions into a single write transaction?this optimization is best implemented in the originating master. PI7C7300D does not merge bytes on separate masked write transactions to the same dword address?this optimization is also best implemented in the originating master. PI7C7300D does not collapse sequential write transactions to the same address into a single write transaction?the pci local bus specification does not permit this combining of transactions. 6.2 general ordering guidelines independent transactions on primary and sec ondary buses have a relationship only when those transactions cross PI7C7300D. the following general ordering guidelines govern transactions crossing PI7C7300D: the ordering relationship of a transaction with respect to other transactions is determined when the transaction completes, that is, when a transaction ends with a termination other than target retry. requests terminated with target retry can be accepted and completed in any order with respect to other transactions that have been terminated with target retry. if the order of completion of delayed requests is important, the initiator should not start a second delayed transaction until the first one has been completed. if more than one delayed transaction is initiated, the initia tor should repeat all delayed transaction requests, using some fairness algorithm. re peating a delayed transaction cannot be contingent on completion of another delayed transaction. otherwise, a deadlock can occur. write transactions flowing in one dir ection have no ordering requirements with respect to write transactions flowing in the other direction. PI7C7300D can accept posted write transactions on both interfaces at the same time, as well as initiate posted write transactions on both interfaces at the same time. the acceptance of a posted memory write tr ansaction as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. this is true for PI7C7300D and must also be true for other bus agents. otherwise, a deadlock can occur. PI7C7300D accepts posted write transactions, regardless of the state of completion of any delayed transactions being forwarded across PI7C7300D. 6.3 ordering rules table 6-1 shows the ordering relationships of all th e transactions and refers by number to the ordering rules that follow. table 6-1 summary of transaction ordering pass posted write delayed read request delayed write request delayed read completion delayed write completion posted write no 1 yes 5 yes 5 yes 5 yes 5 delayed read request no 2 no no yes yes
PI7C7300D 3-port pci-to-pci bridge page 51 of 107 pericom semiconductor november 2005 - revision 1.01 pass posted write delayed read request delayed write request delayed read completion delayed write completion delayed write request no 4 no no yes yes delayed read completion no 3 yes yes no no delayed write completion yes yes yes no no note: the superscript accompanying some of the ta ble entries refers to any applicable ordering rule listed in this section. many entries are not governed by these ordering rules; therefore, the implementation can choose whether or not the transactions pass each other. the entries without superscripts reflect the PI7C7300D?s implementation choices. the following ordering rules describe the trans action relationships. each ordering rule is followed by an explanation, and the orde ring rules are referred to by number in table 6-1 . these ordering rules apply to posted write transactions, delayed write and read requests, and delayed write and read completion transactions crossing PI7C7300D in the same direction. note that delayed completion transactions cross PI7C7300D in the direction opposite that of the corresponding delayed requests. 1. posted write transactions must complete on the target bus in the order in which they were received on the initiator bus. the subs equent posted write transaction can be setting a flag that covers the data in the first posted write transaction; if the second transaction were to complete before the fi rst transaction, a device checking the flag could subsequently consume stale data. 2. a delayed read request traveling in the same direction as a previously queued posted write transaction must push the posted write data ahead of it. the posted write transaction must complete on the target bus before the delayed read request can be attempted on the target bus. the read trans action can be to the same location as the write data, so if the read transaction were to pass the write transaction, it would return stale data. 3. a delayed read completion must ??pull?? ahead of previously queued posted write data traveling in the same direction. in this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of PI7C7300D as the target of the write transaction. the posted write transaction must complete to the target before the read data is returned to the initiator. the read transaction can be a reading to a status register of the initiator of the posted write data and therefore should not complete until the write transaction is complete. 4. delayed write requests cannot pass previ ously queued posted write data. for posted memory write transactions, the delayed write transaction can set a flag that covers the data in the posted write transaction. if the delayed write request were to complete before the earlier posted write transac tion, a device checking the flag could subsequently consume stale data. 5. posted write transactions must be give n opportunities to pass delayed read and write requests and completions. otherwise, deadlocks may occur when some bridges which support delayed transactions and ot her bridges which do not support delayed transactions are being used in the same system. a fairness algorithm is used to arbitrate between the posted write queue and the delayed transaction queue.
PI7C7300D 3-port pci-to-pci bridge page 52 of 107 pericom semiconductor november 2005 - revision 1.01 6.4 data synchronization data synchronization refers to the relati onship between interrupt signaling and data delivery. the pci local bus specification, revision 2.2 , provides the following alternative methods for synchronizing data and interrupts: the device signaling the interrupt performs a read of the data just written (software). the device driver performs a read operation to any register in the interrupting device before accessing data written by the device (software). system hardware guarantees that write bu ffers are flushed before interrupts are forwarded. PI7C7300D does not have a hardware mechan ism to guarantee data synchronization for posted write transactions. therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written (or some other location along the same path), or from the device driver to one of the device registers. 7 error handling PI7C7300D checks, forwards, and generates parity on both the primary and secondary interfaces. to maintain tran sparency, PI7C7300D always tr ies to forward the existing parity condition on one bus to the other bus, along with address and data. pi7c100 always attempts to be transparent when reporting errors, but this is not always possible, given the presence of posted data and delayed transactions. to support error reporting on the pci bus, PI7C7300D implements the following: perr# and serr# signals on both the primary and secondary interfaces primary status and secondary status registers the device-specific p_serr# event disable register this chapter provides detailed information about how PI7C7300D handles errors. it also describes error status reporting and error operation disabling. 7.1 address parity errors PI7C7300D checks address parity for all tran sactions on both buses, for all address and all bus commands. when PI7C7300D detects an address parity error on the primary interface, the followi ng events occur: if the parity error response bit is set in the command register, PI7C7300D does not claim the transaction with p_devsel#; this may allow the transaction to terminate in a master abort. if parity error response bit is not set, PI7C7300D proceeds normally and accepts the transaction if it is directed to or across PI7C7300D. PI7C7300D sets the detected parity error bit in the status register. PI7C7300D asserts p_serr# and sets signaled system error bit in the status register, if both the following conditions are met:
PI7C7300D 3-port pci-to-pci bridge page 53 of 107 pericom semiconductor november 2005 - revision 1.01 - the serr# enable bit is set in the command register. - the parity error response bit is set in the command register. when PI7C7300D detects an address parity error on the secondary interface, the following events occur: if the parity error response bit is set in the bridge control register, PI7C7300D does not claim the transaction with s1_devsel# or s2_devsel#; this may allow the transaction to terminate in a master abort. if parity error response bit is not set, PI7C7300D proceeds normally and accepts trans action if it is directed to or across PI7C7300D. PI7C7300D sets the detected parity error bit in the secondary status register. PI7C7300D asserts p_serr# and sets signaled system error bit in status register, if both of the following conditions are met: - the serr# enable bit is set in the command register. - the parity error response bit is set in the bridge control register. 7.2 data parity errors when forwarding transactions, PI7C7300D atte mpts to pass the data parity condition from one interface to the other unchanged, when ever possible, to allow the master and target devices to handle the error condition. the following sections describe, for each type of transaction, the sequence of events that occurs when a parity error is detected and the way in which the parity condition is forwarded across PI7C7300D. 7.2.1 configuration write transactions to configuration space when PI7C7300D detects a data parity error during a type 0 configuration write transaction to PI7C7300D configurati on space, the following events occur: if the parity error response bit is set in the command register, PI7C7300D asserts p_trdy# and writes the data to the configuration register. PI7C7300D also asserts p_perr#. if the parity error response bit is not set, PI7C7300D does not assert p_perr#. PI7C7300D sets the detected parity error bit in the status register, regardless of the state of the parity error response bit. 7.2.2 read transactions when PI7C7300D detects a parity error during a read transaction, the target drives data and data parity, and the initiator checks parity and conditionally asserts perr#. for downstream transactions, when PI7C7300D detects a read data parity error on the secondary bus, the following events occur:
PI7C7300D 3-port pci-to-pci bridge page 54 of 107 pericom semiconductor november 2005 - revision 1.01 PI7C7300D asserts s_perr# two cycles following the data transfer, if the secondary interface parity error response bit is set in the bridge control register. PI7C7300D sets the detected parity error bit in the secondary status register. PI7C7300D sets the data parity detected bit in the secondary status register, if the secondary interface parity error response bit is set in the bridge control register. PI7C7300D forwards the bad parity with the data back to the in itiator on the primary bus. if the data with the bad parity is pre-fetched and is not read by the initiator on the primary bus, the data is discarded and the data with bad parity is not returned to the initiator. PI7C7300D completes the transaction normally. for upstream transactions, when PI7C7300D detects a read data parity error on the primary bus, the follo wing events occur: PI7C7300D asserts p_perr# two cycles following the data transfer, if the primary interface parity error response bit is set in the command register. PI7C7300D sets the detected parity error bit in the primary status register. PI7C7300D sets the data parity detected bit in the primary status register, if the primary interface parity-error-response b it is set in the command register. PI7C7300D forwards the bad parity with the data back to the initiator on the secondary bus. if the data with the bad parity is pre-fetched and is not read by the initiator on the secondary bus, the data is discarded and the data with bad parity is not returned to the initiator. PI7C7300D completes the transaction normally. PI7C7300D returns to the initiato r the data and parity that was received from the target. when the initiator detects a parity error on this read data and is enabled to report it, the initiator asserts perr# two cycles after the data transfer occurs. it is assumed that the initiator takes responsibility for handling a pa rity error condition; therefore, when PI7C7300D detects perr# asserted while re turning read data to the initiator, PI7C7300D does not take any further action and completes the transaction normally. 7.2.3 delayed write transactions when PI7C7300D detects a data parity error during a delayed write transaction, the initiator drives data and data parity, and the target checks parity a nd conditionally asserts perr#. for delayed write transactions, a parity error can occur at the following times: during the original delayed write request transaction when the initiator repeats the delayed write request transaction when PI7C7300D completes the delayed write transaction to the target when a delayed write transaction is normally queued, the address, command, address parity, data, byte enable bits, and data parity are all captured and a target retry is returned to the initiator. when PI7C7300D detects a pa rity error on the write data for the initial delayed write request transaction, the following events occur:
PI7C7300D 3-port pci-to-pci bridge page 55 of 107 pericom semiconductor november 2005 - revision 1.01 if the parity-error-response bit corresponding to the initiator bus is set, PI7C7300D asserts trdy# to the initiator and the transaction is not queued. if multiple data phases are requested, stop# is also asserted to cause a target disconnect. two cycles after the data transfer, PI7C7300D also asserts perr#. if the parity-error-response bit is not set, pi 7c7300d returns a target retry. it queues the transaction as usual. PI7C7300D does not assert perr#. in this case, the initiator repeats the transaction. PI7C7300D sets the detected-parity-error bit in the status register corresponding to the initiator bus, regardless of the st ate of the parity-error-response bit. note: if parity checking is turned off and data parity errors have occurred for queued or subsequent delayed write transactions on the initiator bus, it is possible that the initiator?s re-attempts of the write transaction may not match the original queued delayed write information contained in the delayed transaction queue. in this case, a master timeout condition may occur, possibly resulting in a system error (p_serr# assertion). for downstream transactions, when PI7C7300D is delivering data to the target on the secondary bus and s_perr# is asserted by the target, the following events occur: PI7C7300D sets the secondary interface data parity detected bit in the secondary status register, if the secondary parity erro r response bit is set in the bridge control register. PI7C7300D captures the parity error conditi on to forward it back to the initiator on the primary bus. similarly, for upstream transactions, when PI7C7300D is delivering data to the target on the primary bus and p_perr# is asserted by the target, the follo wing events occur: PI7C7300D sets the primary inte rface data-parity-detected bit in the status register, if the primary parity-error-response bit is set in the command register. PI7C7300D captures the parity error conditi on to forward it back to the initiator on the secondary bus. a delayed write transaction is completed on the initiator bus when the initiator repeats the write transaction with the same address, command, data, and byte enable bits as the delayed write command that is at the head of the posted data queue. note that the parity bit is not compared when determining whether the transaction matches those in the delayed transaction queues. two cases must be considered: when parity error is detected on the initiator bus on a subsequent re-attempt of the transaction and was not detected on the target bus when parity error is forwarded back from the target bus for downstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C7300D has write status to return, the follo wing events occur: PI7C7300D first asserts p_trdy# and then asserts p_perr# two cycles later, if the primary interface parity-error-response b it is set in the command register.
PI7C7300D 3-port pci-to-pci bridge page 56 of 107 pericom semiconductor november 2005 - revision 1.01 PI7C7300D sets the primary interface parity-error-detected bit in the status register. because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue. similarly, for upstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C7300D has write status to return, the follo wing events occur: PI7C7300D first asserts s1_trdy# or s2_trdy# and then asserts s_perr# two cycles later, if the secondary interface pa rity-error-response bit is set in the bridge control register (offset 3ch). PI7C7300D sets the secondary interface par ity-error-detected bit in the secondary status register. because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue. for downstream transactions, where the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: PI7C7300D asserts p_perr# two cycles after the data transfer, if the following are both true: - the parity-error-response bit is set in the command register of the primary interface. - the parity-error-response bit is set in the bridge control register of the secondary interface. PI7C7300D completes the transaction normally. for upstream transactions, when the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: PI7C7300D asserts s_perr# two cycles after the data transfer, if the following are both true: - the parity error response bit is set in the command register of the primary interface. - the parity error response bit is set in th e bridge control register of the secondary interface. PI7C7300D completes the transaction normally. 7.2.4 posted write transactions during downstream posted write transactions, when PI7C7300D responds as a target, it detects a data parity error on the initiator (primary) bus and the following events occur: PI7C7300D asserts p_perr# two cycles after the data transfer, if the parity error response bit is set in the command register of primary interface. PI7C7300D sets the parity error detected bit in the status register of the primary interface. PI7C7300D captures and forwards the bad parity condition to the secondary bus. PI7C7300D completes the transaction normally.
PI7C7300D 3-port pci-to-pci bridge page 57 of 107 pericom semiconductor november 2005 - revision 1.01 similarly, during upstream posted write transactions, when PI7C7300D responds as a target, it detects a data parity error on th e initiator (secondary) bus, the following events occur: PI7C7300D asserts s_perr# two cycles after the data transfer, if the parity error response bit is set in the bridge control register of the secondary interface. PI7C7300D sets the parity error detected bit in the status register of the secondary interface. PI7C7300D captures and forwards the bad parity condition to the primary bus. PI7C7300D completes the transaction normally. during downstream write transactions, when a data parity error is reported on the target (secondary) bus by the target?s assertion of s_perr#, the following events occur: PI7C7300D sets the data parity detected bit in the status register of secondary interface, if the parity error response bit is set in the bridge control register of the secondary interface. PI7C7300D asserts p_serr# and sets the signaled system error bit in the status register, if all the following conditions are met: - the serr# enable bit is set in the command register. - the posted write parity error bit of p_serr# event disable register is not set. - the parity error response bit is set in th e bridge control register of the secondary interface. - the parity error response bit is set in the command register of the primary interface. - PI7C7300D has not detected the parity error on the primary (initiator) bus which the parity error is not forwarded from the primary bus to the secondary bus. during upstream write transactions, when a data parity error is reported on the target (primary) bus by the target?s assertion of p_perr#, the follo wing events occur: PI7C7300D sets the data parity detected bit in the status register, if the parity error response bit is set in the command re gister of the primary interface. PI7C7300D asserts p_serr# and sets the signaled system error bit in the status register, if all the following conditions are met: - the serr# enable bit is set in the command register. - the parity error response bit is set in th e bridge control register of the secondary interface. - the parity error response bit is set in the command register of the primary interface. - PI7C7300D has not detected the parity error on the secondary (initiator) bus which the parity error is not forwarded from the secondary bus to the primary bus. assertion of p_serr# is used to signal the parity error condition when the initiator does not know that the error occurred. because th e data has already been delivered with no errors, there is no other way to signal this information back to the initiator. if the parity error has forwarded from the initiating bus to the target bus, p_serr# will not be asserted.
PI7C7300D 3-port pci-to-pci bridge page 58 of 107 pericom semiconductor november 2005 - revision 1.01 7.3 data parity error reporting summary in the previous sections, the responses of pi 7c7300d to data parity errors are presented according to the type of transaction in progre ss. this section organizes the responses of PI7C7300D to data parity errors according to the status bits that PI7C7300D sets and the signals that it asserts. table 7-1 shows setting the detected parity error bit in the status register, corresponding to the primary interf ace. this bit is set when PI7C7300D detects a parity error on the primary interface. table 7-1 setting the primary in terface detected parity error bit primary detected parity error bit transaction type direction bus where error was detected primary/ secondary parity error response bits 0 read downstream primary x / x 0 read downstream secondary x / x 1 read upstream primary x / x 0 read upstream secondary x / x 1 posted write downstream primary x / x 0 posted write downstream secondary x / x 0 posted write upstream primary x / x 0 posted write upstream secondary x / x 1 delayed write downstream primary x / x 0 delayed write downstream secondary x / x 0 delayed write upstream primary x / x 0 delayed write upstream secondary x / x x = don?t care table 7-2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. this bit is set when PI7C7300D detects a parity error on the secondary interface. table 7-2 setting secondary interface detected parity error bit secondary detected parity error bit transaction type direction bus where error was detected primary/ secondary parity error response bits 0 read downstream primary x / x 1 read downstream secondary x / x 0 read upstream primary x / x 0 read upstream secondary x / x 0 posted write downstream primary x / x 0 posted write downstream secondary x / x 0 posted write upstream primary x / x 1 posted write upstream secondary x / x 0 delayed write downstream primary x / x 0 delayed write downstream secondary x / x 0 delayed write upstream primary x / x 1 delayed write upstream secondary x / x x = don?t care
PI7C7300D 3-port pci-to-pci bridge page 59 of 107 pericom semiconductor november 2005 - revision 1.01 table 7-3 shows setting data parity detected bit in the primary interface?s status register. this bit is set under the following conditions: PI7C7300D must be a master on the primary bus. the parity error response bit in the command register, corresponding to the primary interface, must be set. the p_perr# signal is detected asserted or a parity error is detected on the primary bus. table 7-3 setting primary interface data parity error detected bit primary data parity bit transaction type direction bus where error was detected primary / secondary parity error response bits 0 read downstream primary x / x 0 read downstream secondary x / x 1 read upstream primary 1 / x 0 read upstream secondary x / x 0 posted write downstream primary x / x 0 posted write downstream secondary x / x 1 posted write upstream primary 1 / x 0 posted write upstream secondary x / x 0 delayed write downstream primary x / x 0 delayed write downstream secondary x / x 1 delayed write upstream primary 1 / x 0 delayed write upstream secondary x / x x = don?t care table 7-4 shows setting the data parity detected bit in the status register of secondary interface. this bit is set under the following conditions: the PI7C7300D must be a master on the secondary bus. the parity error response bit must be set in the bridge control register of secondary interface. the s_perr# signal is detected asserted or a parity error is detected on the secondary bus. table 7-4 setting secondary interface data parity error detected bit secondary detected parity detected bit transaction type direction bus where error was detected primary / secondary parity error response bits 0 read downstream primary x / x 1 read downstream secondary x / 1 0 read upstream primary x / x 0 read upstream secondary x / x 0 posted write downstream primary x / x 1 posted write downstream secondary x / 1 0 posted write upstream primary x / x 0 posted write upstream secondary x / x 0 delayed write downstream primary x / x 1 delayed write downstream secondary x / 1 0 delayed write upstream primary x / x 0 delayed write upstream secondary x / x x= don?t care
PI7C7300D 3-port pci-to-pci bridge page 60 of 107 pericom semiconductor november 2005 - revision 1.01 table 7-5 shows assertion of p_perr#. this si gnal is set under the following conditions: PI7C7300D is either the target of a write transaction or the initiator of a read transaction on the primary bus. the parity-error-response bit must be set in the command register of primary interface. PI7C7300D detects a data parity error on the primary bus or detects s_perr# asserted during the completion phase of a downstream delayed write transaction on the target (secondary) bus. table 7-5 assertion of p_perr# p_perr# transaction type direction bus where error was detected primary/ secondary parity error response bits 1 (de-asserted) read downstream primary x / x 1 read downstream secondary x / x 0 (asserted) read upstream primary 1 / x 1 read upstream secondary x / x 0 posted write downstream primary 1 / x 1 posted write downstream secondary x / x 1 posted write upstream primary x / x 1 posted write upstream secondary x / x 0 delayed write downstream primary 1 / x 0 2 delayed write downstream secondary 1 / 1 1 delayed write upstream primary x / x 1 delayed write upstream secondary x / x x = don?t care 2 the parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
PI7C7300D 3-port pci-to-pci bridge page 61 of 107 pericom semiconductor november 2005 - revision 1.01 table 7-6 shows assertion of s_perr# that is set under the following conditions: PI7C7300D is either the target of a write transaction or the initiator of a read transaction on the secondary bus. the parity error response bit must be set in the bridge control register of secondary interface. PI7C7300D detects a data parity error on the secondary bus or detects p_perr# asserted during the completion phase of an upstream delayed write transaction on the target (primary) bus.
PI7C7300D 3-port pci-to-pci bridge page 62 of 107 pericom semiconductor november 2005 - revision 1.01 table 7-6 assertion of s_perr# s_perr# transaction type direction bus where error was detected primary/ secondary parity error response bits 1 (de-asserted) read downstream primary x / x 0 (asserted) read downstream secondary x / 1 1 read upstream primary x / x 1 read upstream secondary x / x 1 posted write downstream primary x / x 1 posted write downstream secondary x / x 1 posted write upstream primary x / x 0 posted write upstream secondary x / 1 1 delayed write downstream primary x / x 1 delayed write downstream secondary x / x 0 2 delayed write upstream primary 1 / 1 0 delayed write upstream secondary x / 1 x = don?t care 2 the parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. table 7-7 shows assertion of p_serr#. this si gnal is set under the following conditions: PI7C7300D has detected p_perr# asserted on an upstream posted write transaction or s_perr# asserted on a downstream posted write transaction. PI7C7300D did not detect the parity error as a target of the posted write transaction. the parity error response bit on the command register and the parity error response bit on the bridge control register must both be set. the serr# enable bit must be set in the command register. table 7-7 assertion of p_ serr# for data parity errors p_serr# transaction type direction bus where error was detected primary / secondary parity error response bits 1 (de-asserted) read downstream primary x / x 1 read downstream secondary x / x 1 read upstream primary x / x 1 read upstream secondary x / x 1 posted write downstream primary x / x 0 2 (asserted) posted write downstream secondary 1 / 1 0 3 posted write upstream primary 1 / 1 1 posted write upstream secondary x / x 1 delayed write downstream primary x / x 1 delayed write downstream secondary x / x 1 delayed write upstream primary x / x 1 delayed write upstream secondary x / x x = don?t care 2 the parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. 3 the parity error was detected on the target (pri mary) bus but not on the initiator (secondary) bus.
PI7C7300D 3-port pci-to-pci bridge page 63 of 107 pericom semiconductor november 2005 - revision 1.01 7.4 system error (serr#) reporting PI7C7300D uses the p_serr# signal to repor t conditionally a number of system error conditions in addition to the special case pa rity error conditions described in section 7.2.3. whenever assertion of p_serr# is discussed in this document, it is assumed that the following conditions apply: for PI7C7300D to assert p_serr# for any reason, the serr# enable bit must be set in the command register. whenever PI7C7300D asserts p_serr#, PI7C7300D must also set the signaled system error bit in the status register. in compliance with the pci-to-pci bridge architecture specification, PI7C7300D asserts p_serr# when it detects the secondary serr# input, s_serr#, asserted and the serr# forward enable bit is set in the bridge control register. in addition, PI7C7300D also sets the received system erro r bit in the secondary status register. PI7C7300D also conditionally asserts p_serr# for any of the following reasons: target abort detected during posted write transaction master abort detected during posted write transaction posted write data discarded after 2 24 (default) attempts to deliver (2 24 target retries received) parity error reported on target bus during posted write transaction (see previous section) delayed write data discarded after 2 24 (default) attempts to deliver (2 24 target retries received) delayed read data cannot be transferred from target after 2 24 (default) attempts (2 24 target retries received) master timeout on delayed transaction the device-specific p_serr# status register reports the reason for the assertion of p_serr#. most of these events have add itional device-specific disable bits in the p_serr# event disable register that make it possible to mask out p_serr# assertion for specific events. the master timeout condition has a serr# enable b it for that event in the bridge control register and therefore does not have a device-specific disable bit. 8 exclusive access this chapter describes the use of the lock # signal to implement exclusive access to a target for transactions that cross PI7C7300D.
PI7C7300D 3-port pci-to-pci bridge page 64 of 107 pericom semiconductor november 2005 - revision 1.01 8.1 concurrent locks the primary and secondary bus lock mechanisms operate concurrently except when a locked transaction crosses PI7C7300D. a primary master can lock a primary target without affecting the status of the lock on the secondary bus, and vice versa. this means that a primary master can lock a primary target at the same time that a secondary master locks a secondary target. 8.2 acquiring exclusive access across PI7C7300D for any pci bus, before acquiring access to th e lock# signal and starting a series of locked transactions, th e initiator must first check that both of the following conditions are met: the pci bus must be idle. the lock# signal must be de-asserted. the initiator leaves the lock# signal de-asserted during the address phase and asserts lock# one clock cycle later. once a data tr ansfer is completed from the target, the target lock has been achieved. 8.2.1 locked transactions in dowstream direction locked transactions can cross PI7C7300D only in the downstream direction, from the primary bus to the secondary bus. when the target resides on another pci bus, the master must acquire not only the lock on its own pci bus but also the lock on every bus between its bus and the target?s bus. when PI7C7300D detects on the primary bus, an initial locked trans action intended for a target on the secondary bus, PI7C7300D samples the address, transaction type, byte enable bits, and parity, as described in section 4.6.4 . it also samples the lock signal. if there is a lock established between 2 ports or the target bus is already locked by another master, then the current lock cycle is retried without forwar d. because a target retry is signaled to the initiator, the initiator must relinquish the lock on the primary bus, and therefore the lock is not yet established. the first locked transaction must be a memo ry read transaction. subsequent locked transactions can be memory read or memory write transactions. posted memory write transactions that are a part of the locked transaction sequence are still posted. memory read transactions that are a pa rt of the locked transaction sequence are not pre-fetched. when the locked delayed memory read request is queued, PI7C7300D does not queue any more transactions until th e locked sequence is finished . PI7C7300D signals a target retry to all transactions initiated subsequent to the locked read transaction that are intended for targets on the other side of PI7C7300D. PI7C7300D allows any transactions queued before the locked transaction to complete before initiating the locked transaction.
PI7C7300D 3-port pci-to-pci bridge page 65 of 107 pericom semiconductor november 2005 - revision 1.01 when the locked delayed memory read reque st transaction moves to the head of the delayed transaction queue, PI7C7300D initiate s the transaction as a locked read transaction by de-asserting lock# on the targ et bus during the first address phase, and by asserting lock# one cycle later. if lock# is already asserted (used by another initiator), PI7C7300D waits to request access to the secondary bus until lock# is de- asserted when the target bus is idle. note that the existing lock on the target bus could not have crossed PI7C7300D. otherwise, the pending queued locked transaction would not have been queued. when PI7C7300D is able to complete a data transfer with the locked read transaction, the lock is established on the secondary bus. when the initiator repeats the locked read transaction on the primary bus with the same address, transaction type, and byte enable bits, PI7C7300D transfers the read data back to the initiator, and the lock is then also established on the primary bus. for PI7C7300D to recognize and respond to th e initiator, the initiator?s subsequent attempts of the read transaction must use the locked transacti on sequence (de-assert lock# during address phase, and assert lock# one cycle later). if the lock# sequence is not used in subsequent attemp ts, a master timeout condition may result. when a master timeout condition occurs, se rr# is conditionally asserted (see section 7.4 ), the read data and queued read transaction are discarded, and the lock# signal is de-asserted on the target bus. once the intended target has been locked, any subsequent locked transactions initiated on the initiator bus that are forwarded by pi7c 7300d are driven as locked transactions on the target bus. the first transaction to establish lock# must be memory read. if the first transaction is not memory read, the following transactions behave accordingly: - type 0 configuration read/write induces master abort - type 1 configuration read/write induces master abort - i/o read induces master abort - i/o write induces master abort - memory write induces master abort when PI7C7300D receives a target abort or a master abort in response to the delayed locked read transaction, this status is passed back to the initiator, and no locks are established on either the target or th e initiator bus. PI7C7300D resumes forwarding unlocked transactions in both directions. 8.2.2 locked transaction in upstream direction PI7C7300D ignores upstream lock and tr ansactions. PI7C7300D will pass these transactions as normal transactions without lock established. 8.3 ending exclusive access
PI7C7300D 3-port pci-to-pci bridge page 66 of 107 pericom semiconductor november 2005 - revision 1.01 after the lock has been acquired on both initiator and target buses, PI7C7300D must maintain the lock on the target bus for any subsequent locked transactions until the initiator relinquishes the lock. the only time a target-retry causes the lock to be relinquished is on the first transaction of a locked sequence. on subsequent transac tions in the sequence, the target retry has no effect on the status of the lock signal. an established target lock is maintain ed until the initiator re linquishes the lock. PI7C7300D does not know whether the current transaction is the last one in a sequence of locked transactions until the initiator de-asserts the lock# signal at end of the transaction. when the last locked transaction is a delayed transaction, PI7C7300D has already completed the transaction on the target bus. in this example, as soon as PI7C7300D detects that the initiator has relinquished the lock# signal by sampling it in the de- asserted state while frame# is deasserted, PI7C7300D de-asserts the lock# signal on the target bus as soon as possible. because of this behavior, lock# may not be de- asserted until several cycles after the last locked transaction has been completed on the target bus. as soon as PI7C7300D has de-asserted lock# to indicate the end of a sequence of locked transactions, it resumes forwarding unlocked transactions. when the last locked transaction is a posted write transaction, PI7C7300D de-asserts lock# on the target bus at the end of the tr ansaction because the lock was relinquished at the end of the write transaction on the initiator bus. when PI7C7300D receives a target abort or a master abort in response to a locked delayed transaction, PI7C7300D returns a target abort or a master abort when the initiator repeats the locked transaction. the initiator must then deassert lock# at the end of the transaction. PI7C7300D sets the appropriate status bits, flagging the abnormal target termination condition (see section 4.8 ). normal forwarding of unlocked posted and delayed transactions is resumed. when PI7C7300D receives a target abort or a ma ster abort in response to a locked posted write transaction, PI7C7300D cannot pass back that status to the initiator. PI7C7300D asserts serr# on the initiator bus when a targ et abort or a master abort is received during a locked posted write transaction, if the serr# enable bit is set in the command register. signal serr# is asserted for the master abort condition if the master abort mode bit is set in the bridge control register (see section 7.4 ). 9 pci bus arbitration PI7C7300D must arbitrate for use of the primary bus when forwarding upstream transactions. also, it must arbitrate for use of the secondary bus when forwarding downstream transactions. the arbiter for the primary bus resides external to PI7C7300D, typically on the motherboard. for the secondary pci bus, PI7C7300D implements an internal arbiter. this arbiter can be disabled , and an external arbiter can be used instead. this chapter describes primary and secondary bus arbitration.
PI7C7300D 3-port pci-to-pci bridge page 67 of 107 pericom semiconductor november 2005 - revision 1.01 9.1 primary pci bus arbitration PI7C7300D implements a request output pin, p_req#, and a grant input pin, p_gnt#, for primary pci bus arbitration. PI7C7300D asserts p_req# when forwarding transactions upstream; that is, it acts as in itiator on the primary pci bus. as long as at least one pending transaction resides in the queues in the upstream direction, either posted write data or delayed transaction requests, PI7C7300D keeps p_req# asserted. however, if a target retry, target disconnect, or a target abort is received in response to a transaction initiated by PI7C7300D on the primary pci bus, PI7C7300D de-asserts p_req# for two pci clock cycles. for all cycles through the bridge, p_req# is not asserted until the transaction request has been completely queued. when p_gnt# is asserted low by the primary bus arbiter after PI7C7300D has asserted p_req#, PI7C7300D initiates a transaction on the primary bus during the next pci clock cycle. when p_gnt# is asserted to PI7C7300D when p_req# is not asserted, PI7C7300D parks p_ad, p_cbe, and p_par by driving them to valid logic levels. when the primary bus is parked at PI7C7300D and PI7C7300D has a transaction to initiate on the primary bus, PI7C7300D starts the transaction if p_gnt# was assert ed during the previous cycle. 9.2 secondary pci bus arbitration PI7C7300D implements an internal secondary pci bus arbiter. this arbiter supports eight external masters on secondary 1 and seven external masters on secondary 2 in addition to PI7C7300D. the internal arbiter can be disabled, and an external arbiter can be used instead for secondary bus arbitration. 9.2.1 secondary busarbitration using the internal arbiter to use the internal arbiter, the secondary bus arbiter enable pin, s_cfn#, must be tied low. PI7C7300D has eight/seven secondary bus 1/2 request input pins, s1_req#[7:0], s2_req#[6:0], and has eight/seven secondary bus 1/2 output grant pins, s1_gnt#[7:0], s2_gnt#[6:0], to support external secondary bus masters. the secondary bus request and grant signals are connected internally to the arbiter and are not brought out to external pins when s_cfn# is high. the secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each set taking care of 8 requests/ grants. each set of masters can be assigned to a high priority group and a low priority group. the low priority group as a whole represents one entry in the high priority group; that is, if the high priority group consists of n masters, then in at least every n+1 transactions the highest priority is assigned to the low priority group. priority rotates evenly among the low priority group. therefore, members of the high priority group can be serviced n transactions out of n+1, while one member of the low priority group is serviced once every n+1 transactions. error! reference source not found. shows an example of an internal arbiter where four masters, including PI7C7300D, are in the high priority group, and five masters are in the low priority group. using this example, if all requests are always asserted, the highest priority rotates among
PI7C7300D 3-port pci-to-pci bridge the masters in the following fashion (high priority members are given in italics, low priority members, in boldface type): b, m0, m1, m2, m3 , b, m0, m1, m2, m4 , b, m0, m1, m2, m5 , b, m0, m1, m2, m6 , b, m0, m1, m2, m7 and so on. figure 9-1 secondary arbiter example each bus master, including PI7C7300D, can be configured to be in either the low priority group or the high priority group by setting th e corresponding priority bit in the arbiter- control register. the arbiter-control register is located at offset 40h. each master has a corresponding bit. if the bit is set to 1, the master is assigned to the high priority group. if the bit is set to 0, the master is assigned to the low priority group. if all the masters are assigned to one group, the algorithm defaults to a straight rotating priority among all the masters. after reset, all external masters are assigned to the low priority group, and PI7C7300D is assigned to the high priority group. PI7C7300D receive s highest priority on the target bus every other transaction, and priority rotates evenly among the other masters. priorities are re-evaluated every time s1_f rame# or s2_frame# is asserted at the start of each new transaction on the seconda ry pci bus. from this point until the time that the next transaction starts, the arbiter asserts the grant signal corresponding to the highest priority request that is asserted. if a grant for a particular request is asserted, and a higher priority request subsequently assert s, the arbiter de-asserts the asserted grant signal and asserts the grant corresponding to th e new higher priority request on the next pci clock cycle. when priorities are re-evaluated, the highest priority is assigned to the next highest priority master relative to the master that initiated the previous transaction. the master that initiated the la st transaction now has the lowest priority in its group. if PI7C7300D detects that an initiator has fa iled to assert s1_frame# or s2_frame# after 16 cycles of both grant a ssertion and a secondary idle bus condition, the arbiter de- asserts the grant. that master does not r eceive any more grants until it deasserts its request for at least one pci clock cycle. to prevent bus contention, if the secondary pc i bus is idle, the arbiter never asserts one grant signal in the same pci cycle in which it deasserts another. it de-asserts one grant and asserts the next grant, no earlier than one pci clock cycle later. if the secondary pci bus is busy, that is, either s1_frame# (s2_frame#) or s1_irdy# (s2_irdy#) is asserted, the arbiter can de-assert one grant and assert another grant during the same pci clock cycle. page 68 of 107 pericom semiconductor november 2005 - revision 1.01
PI7C7300D 3-port pci-to-pci bridge page 69 of 107 pericom semiconductor november 2005 - revision 1.01 9.2.2 preemption preemption can be programmed to be either on or off, with the default to on (offset 4ch, bit 31=0). time-to-preempt can be programmed to 8,16, 32, 64, or 128 (default is 32) clocks. if the current master occupies the bus and ot her masters are waiting, the current master will be preempted by removing its grant (gnt#) after the next master waits for the time- to-preempt. 9.2.3 secondary bus arbitration using an external arbiter the internal arbiter is disabled when the secondary bus central function control pin, s_cfn#, is tied high. an external arbiter must then be used. when s_cfn# is tied high, PI7C7300D, reconfigures four pins (two per port) to be external request and grant pins. the s1_gnt#[ 0] and s2_gnt#[0] pins are reconfigured to be the external request pins because they are output. the s1_req#[0] and s2_req#[0] pins are reconfigured to be the external grant pins because they are input. when an external arbiter is used, PI7C7300D uses the s1_gnt#[0] or s2_gnt#[0] pin to request the secondary bus. when the reconfigured s1_req#[0] and s2_req#[0] pin is asserted low after PI7C7300D has asserted s1_gnt#[0] or s2_gnt#[0]. PI7C7300D initiates a transaction on the secondary bus one cycle later. if grant is asserted and PI7C7300D has not asserted the request, PI7C7300D parks ad, cbe and par pins by driving them to valid logic levels. the unused secondary bus grants outputs, s_gnt#[7:1] and s_gnt#[6:1] are driven high. the unused secondary bus requests i nputs, s1_req#[7:1] and s2_req#[6:1], should be pulled high. 9.2.4 bus parking bus parking refers to driving the ad[31:0], cbe[3:0]#, and par lines to a known value while the bus is idle. in general, the device implementing the bus arbiter is responsible for parking the bus or assigning another devi ce to park the bus. a device parks the bus when the bus is idle, its bus grant is asserted, and the device?s request is not asserted. the ad and cbe signals should be driven first, with the par signal driven one cycle later. PI7C7300D parks the primary bus only when p_gnt# is asserted, p_req# is de- asserted, and the primary pci bus is idle. when p_gnt# is de-asserted, PI7C7300D 3- states the p_ad, p_cbe, and p_par signals on the next pci clock cycle. if PI7C7300D is parking the primary pci bus and wants to initiate a transaction on that bus, then PI7C7300D can start the transaction on the next pci clock cycle by asserting p_frame# if p_gnt# is still asserted. if the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last master that used the pci bus. that is, PI7C7300D keeps the secondary bus grant asserted to a particular master until a ne w secondary bus request comes along. after reset, PI7C7300D parks the secondary bus at itself until transactions start occurring on
PI7C7300D 3-port pci-to-pci bridge page 70 of 107 pericom semiconductor november 2005 - revision 1.01 the secondary bus. if the internal arbiter is disabled, PI7C7300D parks the secondary bus only when the reconfigured grant signal, s_req#[0], is asserted and the secondary bus is idle. 10 compact pci hot swap compact pci (cpci) hot swap (picmg 2.1, r1.0) defines a process for installing and removing pci boards form a compact pci system without powering down the system. the PI7C7300D is hot swap friendly silicon that supports all the cpci hot swap capable features and adds support for softwa re connection control. being hot swap friendly, the PI7C7300D supports the following: compliance with pci specification 2.2 tolerates v cc from early power asynchronous reset tolerates precharge voltage i/o buffers meet modi fied v/i requirements limited i/o pin leakage at precharge voltage when the PI7C7300D resides on the compact pci add-in card, the primary bus must be the bus that is inserted into the compact pci system. to perform the hot swap function, the device must be configured according to the cpci hot-swap specifications . for the PI7C7300D, the only path for configuration is through the primary bus. the bridge may not be configured through either secondary buses. if the user chooses to use the secondary buses for insertion, an external register needs to be provided for the hot swap control status register. 11 clocks this chapter provides information about the clocks. 11.1 primary clock inputs PI7C7300D implements a primary clock i nput for the pci interface. the primary interface is synchronized to the primary cloc k input, p_clk, and the secondary interface is synchronized to the secondary clock. the secondary clock is derived internally from the primary clock, p_clk, through an internal pll. PI7C7300D operates at a maximum frequency of 66 mhz. 11.2 secondary clock outputs PI7C7300D has 16 secondary clock outputs, s_cl kout[15:0] that can be used as clock inputs for up to fifteen external secondary bus devices. the s_clkout[15:0] outputs are derived from p_clk. the secondary cloc k edges are delayed from p_clk edges by a minimum of 0ns. this is the rule for using secondary clocks:
PI7C7300D 3-port pci-to-pci bridge page 71 of 107 pericom semiconductor november 2005 - revision 1.01 each secondary clock output is limited to no more than one load. 12 reset this chapter describes the primary interf ace, secondary interface, and chip reset mechanisms. 12.1 primary interface reset PI7C7300D has a reset input, p_reset#. when p_reset# is asserted, the following events occur: PI7C7300D immediately 3-states all prim ary and secondary pci interface signals. PI7C7300D performs a chip reset. registers that have default values are reset. p_reset# asserting and de-asserting e dges can be asynchronous to p_clk and s_clk. PI7C7300D is not accessible duri ng p_reset#. after p_reset# is de- asserted, PI7C7300D remains inaccessible for 16 pci clocks (t rhfa , page 128 of the pci local bus specification rev 2.2) before the first configuration transaction can be accepted. 12.2 secondary interface reset PI7C7300D is responsible for driving the s econdary bus reset signals, s1_reset# and s2_reset#. PI7C7300D asserts s1_reset# or s2_reset# when any of the following conditions is met: signal p_reset# is asserted. signal s1_reset# or s2_reset# remains asserted as long as p_reset# is asserted and does not de-assert until p_reset# is de-asserted. the secondary reset bit in the br idge control register is set. signal s1_reset# or s2_reset# remains asserted until a configuration write operation clears the secondary reset bit. s1_reset# or s2_reset# pin is asserted. when s1_reset# or s2_reset# is asserted, PI7C7300D immediat ely 3-states all the secondary pci interface signals associated with the secondary s1 or s2 port. the s1_reset# or s2_reset# in asserting and de-asserting edges can be asynchronous to p_clk. when s1_reset# or s2_reset# is assert ed, all secondary pci interface control signals, including the secondary grant outputs, are immediately 3-stated. signals s1_ad, s1_cbe[3:0]#, s1_par (s2_ad, s2_cbe[3:0]#, s2_par) are driven low for the duration of s1_reset# (s2_reset#) assertion. all posted write and delayed transaction data buffers are reset. therefore, any transactions residing inside the buffers at the time of secondary reset are discarded.
PI7C7300D 3-port pci-to-pci bridge page 72 of 107 pericom semiconductor november 2005 - revision 1.01 when s1_reset# or s2_reset# is asserted by means of the secondary reset bit, PI7C7300D remains accessible dur ing secondary interface rese t and continues to respond to accesses to its configuration space from the primary interface. 13 supported commands the pci command set is given below for the primary and secondary interfaces. 13.1 primary interface p_cbe [3:0] # command action 0000 interrupt acknowledge ignore 0001 special cycle do not claim. ignore. 0010 i/o read 1. if address is within pass through i/o range, claim and pass through. 2. otherwise, do not pass through and do not claim for internal access. 0011 i/o write same as i/o read. 0100 reserved ----- 0101 reserved ----- 0110 memory read 1. if address is within pass through memory range, claim and pass through. 2. if address is within pass through memory mapped i/o range, claim and pass through. 3. otherwise, do not pass through and do not claim for internal access. 0111 memory write same as memory read. 1000 reserved ----- 1001 reserved ----- 1010 configuration read i. type 0 configuration read: if the bridge?s idsel line is asserted, perform function decode and claim if target function is implemented. otherwise, ignore. if claimed, permit access to target function?s configuration regi sters. do not pass through under any circumstances. ii. type 1 configuration read: 1. if the target bus is the bridge?s secondary bus: claim and pass through as a type 0 configuration read. 2. if the target bus is a subordinate bus that exists behind the bridge (but not equal to the secondary bus): claim and pass through as a type 1 configuration read. 3. otherwise, ignore. 1011 configuration write i. type 0 configuration writ e: same as configuration read. ii. type 1 configuration write (not special cycle request): 1. if the target bus is the bridge?s secondary bus: claim and pass through as a type 0 configuration write 2. if the target bus is a subordinate bus that exists behind the bridge (but not equal to the secondary bus): claim and pass through unchanged as a type 1 configuration write. 3. otherwise, ignore. iii. configuration write as special cycle request (device = 1fh, function = 7h)
PI7C7300D 3-port pci-to-pci bridge page 73 of 107 pericom semiconductor november 2005 - revision 1.01 p_cbe [3:0] # command action 1. if the target bus is the bridges secondary bus: claim and pass through as a special cycle. 2. if the target bus is a subordinate bus that exists behind the bridge (but not equal to the secondary bus): claim and pass through unchanged as a type 1 configuration write. 3. otherwise ignore 1100 memory read multiple same as memory read 1101 dual address cycle supported 1110 memory read line same as memory read 1111 memory write and invalidate same as memory read 13.2 secondary interface s1_cbe [3:0] # s2_cbe [3:0] # command action 0000 interrupt acknowledge ignore 0001 special cycle do not claim. ignore. 0010 i/o read same as primary interface 0011 i/o write same as i/o read. 0100 reserved ----- 0101 reserved ----- 0110 memory read same as primary interface 0111 memory write same as memory read. 1000 reserved ----- 1001 reserved ----- 1010 configuration read ignore 1011 configuration write i. type 0 configuration write: ignore ii. type 1 configuration write (not special cycle request):ignore iii. configuration write as special cycle request (device = 1fh, function = 7h): 1. if the target bus is the bridge?s primary bus: claim and pass through as a special cycle 2. if the target bus is neither the primary bus nor is it in range of buses defined by the bridge?s secondary and subordinate bus registers: claim and pass through unchanged as a type 1 configuration write. 3. if the target bus is not the bridge?s primary bus, but is in range of buses defined by the bridge?s secondary and subordinate bus registers: ignore. 1100 memory read multiple same as memory read 1101 dual address cycle supported 1110 memory read line same as memory read 1111 memory write and invalidate same as memory read 14 configuration registers as PI7C7300D supports two secondary interf aces, it has two sets of configuration registers that are almost identical and acce ssed through different function numbers. pci configuration defines a 64-byte space (configuration header) to define various attributes of the pci-to-pci bridge as shown below. there are two configuration registers:
PI7C7300D 3-port pci-to-pci bridge page 74 of 107 pericom semiconductor november 2005 - revision 1.01 configuration register 1 and configuration register 2 corresponding to secondary bus 1 and secondary bus 2 interfaces respectivel y. the configuration for the primary interface is implemented through configuration register 1.
PI7C7300D 3-port pci-to-pci bridge page 75 of 107 pericom semiconductor november 2005 - revision 1.01 14.1 configuration register 1 and 2 31-24 23-16 15-8 7-0 address device id vendor id 00h status command 04h class code revision id 08h reserved header type primary la tency timer cache line size 0ch reserved 10h reserved 14h secondary latency timer subordinate bus number secondary bus number primary bus number 18h secondary status i/o limit i/o base 1ch memory limit memory base 20h prefetchable memory limit prefetchable memory base 24h prefetchable base upper 32-bit 28h prefetchable limit upper 32-bit 2ch i/o limit upper 16-bit i/o base upper 16-bit 30h reserved ecp pointer 34h reserved 38h bridge control reserved 3ch arbiter control diagnostic / chip control 40h reserved 44h upstream memory control reserved 48h hot swap switch time slot 4ch upstream (s1 or s2 to p) memory limit upstream (s1 or s2 to p) memory base 50h upstream (s1 or s2 to p) memory base upper 32-bit 54h upstream (s1 or s2 to p) memory limit upper 32-bit 58h reserved 5ch reserved 60h reserved p_serr# event disable 64h reserved secondary clock control 68h reserved 6ch reserved 70h master timeout counter port option 74h retry counter 78h sampling timer 7ch secondary successful i/o read counter 80h secondary successful i/o write counter 84h secondary successful memory read counter 88h secondary successful memory write counter 8ch primary successful i/o read counter 90h primary successful i/o write counter 94h primary successful memory read counter 98h primary successful memory write counter 9ch reserved a0h-afh chassis number slot number next pointer capability id b0h reserved b4h-bfh hot swap control and status next pointer capability id c0h reserved d0h-ffh 14.1.1 vendor id register ? offset 00h bit function type description 15:0 vendor id r/o identifies pericom as vendor of this device. hardwired as 12d8h.
PI7C7300D 3-port pci-to-pci bridge page 76 of 107 pericom semiconductor november 2005 - revision 1.01 14.1.2 device id register ? offset 00h configuration register 1 bit function type description 31:16 device id r/o identifies this device as the PI7C7300D. hardwired as 71e2h. configuration register 2 bit function type description 31:16 device id r/o identifies this device as the PI7C7300D. hardwired as 71e3h. 14.1.3 command register ? offset 04h bit function type description 0 i/o space enable r/w controls response to i/o access on the primary interface 0: ignore i/o transactions on the primary interface 1: enable response to i/o tran sactions on the primary interface reset to 0 1 memory space enable r/w controls response to memory accesses on the primary interface 0: ignore memory transactions on the primary interface 1: enable response to memory tr ansactions on the primary interface reset to 0 2 bus master enable r/w controls ability to operate as a bus master on the primary interface 0: do not initiate memory or i/o transactions on the primary interface and disable response to memory and i/o transactions on secondary 1 interface 1: enables PI7C7300D to operate as a master on the primary interfaces for memory and i/o transactions forwarded from the secondary interface reset to 0 3 special cycle enable r/o no special cycles defined. bit is defined as read only and returns 0 when read 4 memory write and invalidate enable r/o memory write and invalidate not supported. bit is implemented as read only and returns 0 when read (unless forwarding a transaction for another master) 5 vga palette snoop enable r/w controls response to vga compatible palette accesses 0: ignore vga palette accesses on the primary 1: enable positive decoding response to vga palette writes on the primary interface with i/o address bits ad[9:0] equal to 3c6h, 3c8h, and 3c9h (inclusive of isa alias; ad[15:10] are not decoded and may be any value)
PI7C7300D 3-port pci-to-pci bridge page 77 of 107 pericom semiconductor november 2005 - revision 1.01 bit function type description 6 parity error response r/w controls response to parity errors 0: PI7C7300D may ignore any parity errors that it detects and continue normal operation 1: PI7C7300D must take its normal action when a parity error is detected reset to 0 7 wait cycle control r/o controls the ability to perf orm address / data stepping 0: disable address/data steppi ng (affects primary and secondary) 1: enable address/data steppi ng (affects primary and secondary) reset to 0 8 p_serr# enable r/w controls the enable for the p_serr# pin 0: disable the p_serr# driver 1: enable the p_serr# driver reset to 0 9 fast back-to- back enable r/w controls PI7C7300D?s ability to generate fast back-to-back transactions to different devices on the primary interface. 0: no fast back-to-back transactions 1: enable fast back-t o-back transactions reset to 0 15:10 reserved r/o returns 000000 when read 14.1.4 status register ? offset 04h bit function type description 19:16 reserved r/o reset to 0 20 capabilities list r/o set to 1 to enable support for the capability list (offset 34h is the pointer to the data structure) reset to 1 21 66mhz capable r/o set to 1 to enable 66mhz operation on the primary interface reset to 1 22 reserved r/o reset to 0 23 fast back-to- back capable r/o set to 1 to enable decoding of fast back-to-back transactions on the primary interface to different targets reset to 1 24 data parity error detected r/wc set to 1 when p_perr# is asserted and bit 6 of command register is set reset to 0 26:25 devsel# timing r/o devsel# timing (medium decoding) 00: fast devsel# decoding 01: medium devsel# decoding 10: slow devsel# decoding 11: reserved reset to 01
PI7C7300D 3-port pci-to-pci bridge page 78 of 107 pericom semiconductor november 2005 - revision 1.01 bit function type description 27 signaled target abort r/wc set to 1 (by a target device) wh enever a target abort cycle occurs reset to 0 28 received target abort r/wc set to 1 (by a master device) wh enever transactions are terminated with target aborts reset to 0 29 received master abort r/wc set to 1 (by a master) when tran sactions are terminated with master abort reset to 0 30 signaled system error r/wc set to 1 when p_serr# is asserted reset to 0 31 detected parity error r/wc set to 1 when address or data parity error is detected on the primary interface reset to 0 14.1.5 revision id register ? offset 08h bit function type description 7:0 revision r/o indicates revision num ber of device. hardwired to 01h 14.1.6 class code register ? offest 08h bit function type description 15:8 programming interface r/o read as 0 to indicate no programming interfaces have been defined for pci-to-pci bridges 23:16 sub-class code r/o read as 04h to indicate device is pci-to-pci bridge 31:24 base class code r/o read as 06h to indicate device is a bridge device 14.1.7 cache line size register ? offset 0ch bit function type description 7:0 cache line size r/w designates the cache line size for the system and is used when terminating memory write and i nvalidate transactions and when prefetching memory read transactions. only cache line sizes (in units of 4-byte) which are a power of two are valid (only one bit can be set in this register; only 00h, 01h, 02h, 04h, 08h, and 10h are valid values). reset to 0 14.1.8 primary latency timer register ? offset 0ch bit function type description 15:8 primary latency timer r/w this register sets the value for the master latency timer which starts counting when the master asserts frame#. reset to 0
PI7C7300D 3-port pci-to-pci bridge page 79 of 107 pericom semiconductor november 2005 - revision 1.01 14.1.9 header type register ? offset 0ch configuration register 1 bit function type description 23:16 header type r/o read as 81h to designate function 0 (multiple function pci-to-pci bridge for secondary bus s1) configuration register 2 bit function type description 23:16 header type r/o read as 01h to desi gnate function 1 (single function pci-to-pci bridge for secondary bus s2) 14.1.10 primary bus number register ? offset 18h bit function type description 7:0 primary bus number r/w indicates the number of the pci bus to which the primary interface is connected. the value is set in software during configuration. reset to 0 14.1.11 secondary (s1 or s2) bus number register ? offset 18h bit function type description 15:8 secondary (s1 or s2) bus number r/w indicates the number of the pci bus to which the secondary interface (s1 or s2) is connected. the value is set in software during configuration. reset to 0 14.1.12 subordinate (s1 or s2) bus number register ? offset 18h bit function type description 23:16 subordinate (s1 or s2) bus number r/w indicates the number of the pci bus with the highest number that is subordinate to the bridge. the value is set in software during configuration. reset to 0 14.1.13 secondary latency timer register ? offset 18h bit function type description 31:24 secondary latency timer r/w designated in units of pci bus clocks. latency timer checks for master accesses on the secondary bus interfaces that remain unclaimed by any target. reset to 0
PI7C7300D 3-port pci-to-pci bridge page 80 of 107 pericom semiconductor november 2005 - revision 1.01 14.1.14 i/o base register ? offset 1ch bit function type description 3:0 32-bit indicator r/o read as 01h to indicate 32-bit i/o addressing 7:4 i/o base address [15:12] r/w defines the bottom address of th e i/o address range for the bridge to determine when to forward i/o transactions from one interface to the other. the upper 4 bits correspond to address bits [15:12] and are writable. the lower 12 bits corresponding to address bits [11:0] are assumed to be 0. the upper 16 bits corresponding to address bits [31:16] are defined in the i/o base address upper 16 bits address register reset to 0 14.1.15 i/o limit register ? offset 1ch bit function type description 11:8 32-bit indicator r/o read as 01h to indicate 32-bit i/o addressing 15:12 i/o base address [15:12] r/w defines the top address of the i/ o address range for the bridge to determine when to forward i/o tr ansactions from one interface to the other. the upper 4 bits correspond to address bits [15:12] and are writable. the lower 12 bits corresponding to address bits [11:0] are assumed to be fffh. the upper 16 bits corresponding to address bits [31:16] are defined in the i/o base address upper 16 bits address register reset to 0 14.1.16 secondary status register ? offset 1ch bit function type description 20:16 reserved r/o reset to 0 21 66mhz capable r/o set to 1 to enable 66mhz operation on the secondary (s1 or s2) interface reset to 1 22 reserved r/o reset to 0 23 fast back-to- back capable r/o set to 1 to enable decoding of fa st back-to-back transactions on the secondary (s1 or s2) interface to different targets reset to 0 24 data parity error detected r/wc set to 1 when s1_perr# or s2_perr# is asserted and bit 6 of command register is set reset to 0 26:25 devsel# timing r/o devsel# timing (medium decoding) 00: fast devsel# decoding 01: medium devsel# decoding 10: slow devsel# decoding 11: reserved reset to 01
PI7C7300D 3-port pci-to-pci bridge page 81 of 107 pericom semiconductor november 2005 - revision 1.01 bit function type description 27 signaled target abort r/wc set to 1 (by a target device) whenever a target abort cycle occurs on its secondary (s1 or s2) interface reset to 0 28 received target abort r/wc set to 1 (by a master device) whenever transactions on its secondary (s1 or s2) interface are termin ated with target abort reset to 0 29 received master abort r/wc set to 1 (by a master) when transactions on its secondary (s1 or s2) interface are terminated with master abort reset to 0 30 received system error r/wc set to 1 when s1_serr# or s2_serr# is asserted reset to 0 31 detected parity error r/wc set to 1 when address or data parity error is detected on the secondary (s1 or s2) interface reset to 0 14.1.17 memory base register ? offset 20h bit function type description 3:0 r/o lower four bits of register are read only and return 0. reset to 0 15:4 memory base address [15:4] r/w defines the bottom address of an address range for the bridge to determine when to forward memory transactions from one interface to the other. the upper 12 bits correspond to address bits [31:20] and are writable. the lower 20 bits corresponding to address bits [19:0] are assumed to be 0. reset to 0 14.1.18 memory limit register ? offset 20h bit function type description 19:16 r/o lower four bits of register are read only and return 0. reset to 0 31:20 memory limit address [31:20] r/w defines the top address of an address range for the bridge to determine when to forward memory transactions from one interface to the other. the upper 12 bits correspond to address bits [31:20] and are writable. the lower 20 bits corresponding to address bits [19:0] are assumed to be fffffh.
PI7C7300D 3-port pci-to-pci bridge page 82 of 107 pericom semiconductor november 2005 - revision 1.01 14.1.19 prefetchable memory base register ? offset 24h bit function type description 3:0 64-bit addressing r/o indicates 64-bit addressing 0000: 32-bit addressing 0001: 64-bit addressing reset to 1 15:4 prefetchable memory base address [31:20] r/w defines the bottom address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. the upper 12 bits correspond to address bits [31:20] and are writable. the lower 20 bits are assumed to be 0. 14.1.20 prefetchable memory limit register ? offset 24h bit function type description 19:16 64-bit addressing r/o i ndicates 64-bit addressing 0000: 32-bit addressing 0001: 64-bit addressing reset to 1 31:20 prefetchable memory base address [31:20] r/w defines the top address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. the upper 12 bits correspond to address bits [31:20] and are writable. the lower 20 bits are assumed to be fffffh. 14.1.21 prefetchable memory base address upper 32-bits register ? offset 28h bit function type description 31:0 prefetchable memory base address, upper 32-bits [63:32] r/w defines the upper 32-bits of a 64-bit bottom address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. reset to 0 14.1.22 prefetchable memory limit address upper 32-bits register ? offset 2ch bit function type description 31:0 prefetchable memory limit address, upper 32-bits [63:32] r/w defines the upper 32-bits of a 64-bit top address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. reset to 0
PI7C7300D 3-port pci-to-pci bridge page 83 of 107 pericom semiconductor november 2005 - revision 1.01 14.1.23 i/o base address upper 16-bits register ? offset 30h bit function type description 15:0 i/o base address, upper 16-bits [31:16] r/w defines the upper 16-bits of a 32-bit bottom address of an address range for the bridge to determine when to forward i/o transactions from one interface to the other. reset to 0 14.1.24 i/o limit address upper 16-bits register ? offset 30h bit function type description 31:0 i/o limit address, upper 16-bits [31:16] r/w defines the upper 16-bits of a 32-bit top address of an address range for the bridge to determine when to forward i/o transactions from one interface to the other. reset to 0 14.1.25 ecp pointer register ? offset 34h bit function type description 7:0 enhanced capabilities port pointer r/o enhanced capabilities port offset poi nter. read as b0h to indicate that the first item resides at that configuration offset. 14.1.26 bridge control register ? offset 3ch bit function type description 16 parity error response r/w controls the bridge?s response to parity errors on the secondary interface. 0: ignore address and data parity errors on the secondary interface 1: enable parity error reporti ng and detection on the secondary interface reset to 0 17 s1_serr# enable r/w controls the forwarding of s1_serr# or s2_serr# to the primary interface. 0: disable the forwarding of s1_serr# or s2_serr# to primary interface 1: enable the forwarding of s1_serr# or s2_serr# to primary interface reset to 0
PI7C7300D 3-port pci-to-pci bridge page 84 of 107 pericom semiconductor november 2005 - revision 1.01 bit function type description 18 isa enable r/w modifies the bridge?s res ponse to isa i/o addresses, applying only to those addresses falling within the i/ o base and limit address registers and within the first 64kb or pci i/o space. 0: forward all i/o addresses in the range defined by the i/o base and i/o limit registers 1: blocks forwarding of isa i/o addr esses in the range defined by the i/o base and i/o limit registers that are in the first 64kb of i/o space that address the last 768 bytes in each 1kb block. secondary i/o transactions are forwarded upstream if the address falls within the last 768 bytes in each 1kb block reset to 0 19 vga enable r/w controls the bridge?s response to vga compatible addresses. 0: does not forward vga compatible memory and i/o addresses from primary to secondary 1: forward vga compatible memory and i/o addresses from primary to secondary regardless of other settings reset to 0 20 reserved r/o reserved. retu rns 0 when read. reset to 0 21 master abort mode r/w control?s bridge?s behavior res ponding to master aborts on secondary interface. 0: does not report master abor ts (returns ffff_ffffh on reads and discards data on writes) 1: reports master aborts by signaling target abort if possible by the assertion of p_serr# if enabled reset to 0 22 secondary interface reset r/w controls the assertion of s 1_reset# or s2_reset# signal pin on the secondary interface 0: does not force the assertion of s1_reset# or s2_reset# pin 1: forces the assertion of s1_reset# or s2_reset# reset to 0 23 fast back-to- back enable r/w controls bridge?s ability to generate fast back-to-back transactions to different devices on the secondary interface. 0: does not allow fast back-to-back transactions 1: enables fast back-t o-back transactions reset to 0 24 reserved r/w reserved. reset to 0 25 reserved r/w reserved. reset to 0 26 master timeout status r/wc this bit is set to 1 when either the primary master timeout counter or secondary master timeout counter expires. reset to 0 27 discard timer p_serr# enable r/wc this bit is set to 1 and p_serr# is asserted when either the primary discard timer or the secondary s1 or s2 discard timer expire. reset to 0 31-28 reserved r/o reserved. retu rns 0 when read. reset to 0.
PI7C7300D 3-port pci-to-pci bridge page 85 of 107 pericom semiconductor november 2005 - revision 1.01 14.1.27 diagnostic / chip control register ? offset 40h configuration 1 bit function type description 0 reserved r/o reserved. retu rns 0 when read. reset to 0 1 memory write disconnect control r/w controls when the bridge (as a target) disconnects memory write transactions. 0: memory write disconnects at 4kb aligned address boundary 1: memory write disconnects at cache line aligned address boundary reset to 0 3:2 reserved r/o reserved. retu rns 0 when read. reset to 0. 4 memory read flow-through control r/w controls whether the bridge supports memory read flow-through 0: enable 1: disable reset to 0 8:5 reserved r/o reserved. retu rns 0 when read. reset to 0 10:9 test mode for all counters at p and s1 r/o controls the testability of the bridge?s internal counters. the bits are used for chip test only. 00: all bits are exercised 01: byte 1 is exercised 10: byte 2 is exercised 11: byte 3 is exercised reset to 0 15:11 reserved r/o reserved. retu rns 0 when read. reset to 0. configuration 2 bit function type description 0 reserved r/o reserved. retu rns 0 when read. reset to 0 1 memory write disconnect control at s2 r/w controls when the bridge (as a target) disconnects memory write transactions. 0: memory write disconnects at 4kb aligned address boundary 1: memory write disconnects at cache line aligned address boundary reset to 0 3:2 reserved r/o reserved. retu rns 0 when read. reset to 0 4 memory read flow-through control r/w controls whether the bridge supports memory read flow-through 0: enable 1: disable reset to 0 8:5 reserved r/o reserved. retu rns 0 when read. reset to 0 10:9 test mode for all counters at s2 r/o controls the testability of the bridge?s internal counters. the bits are used for chip test only. 00: all bits are exercised 01: byte 1 is exercised 10: byte 2 is exercised 11: byte 3 is exercised reset to 0 15:11 reserved r/o reserved. retu rns 0 when read. reset to 0.
PI7C7300D 3-port pci-to-pci bridge page 86 of 107 pericom semiconductor november 2005 - revision 1.01 14.1.28 arbiter control register ? offset 40h bit function type description 23:16 arbiter control r/w each bit controls whether a secondary bus master is assigned to the high priority group or the low priority group. bits [23:16] correspond to request inputs s1_req[7:0] or s2_req[6:0] 0: low priority 1: high priority reset to 0 24 reserved r/o reserved. retu rns 0 when read. reset to 0 25 priority of secondary interface r/w controls whether the s1 or s2 in terface of the bridge is in the high priority group or the low priority group. 0: low priority 1: high priority reset to 1 26 arbiter park function r/w controls the arbiter?s park function. 0: park to last master 1: park to bridge port s1 or s2 reset to 0 31:27 reserved r/o reserved. retu rns 0 when read. reset to 0. 14.1.29 upstream memory control register ? offset 48h bit function type description 16 upstream (s1 or s2 to p) memory base and limit enable r/w 0: upstream memory is the en tire range except the down stream memory channel 1: upstream memory is confined to upstream memory base and limit (see offset 50 th and 54 th for upstream memory range) reset to 0 17 upstream (s1 or s2 to p) memory prefetchable enable r/w 0: upstream memory is prefetchable at primary 1: upstream memory is not prefetchable at primary reset to 0 31:18 reserved r/o reserved. retu rns 0 when read. reset to 0 14.1.30 hot swap switch time slot register ? offset 4ch bit function type description 27:0 hot swap time slot r/w hot swap time slot (15k pci clocks) reset to 0003a98h
PI7C7300D 3-port pci-to-pci bridge page 87 of 107 pericom semiconductor november 2005 - revision 1.01 bit function type description 30:28 secondary bus master preemption control r/w sets the number of clocks for time-to-preempt after another master request. 000: 32 clocks 001: 8 clocks 010: 16 clocks 011: 64 clocks 100: 128 clocks reset to 000 31 preemption r/w sets preemption. 0: preemption on 1: preemption off reset to 0 14.1.31 upstream (s1 or s2 to p) memory base register ? offset 50h bit function type description 3:0 64 bit addressing r/o 0: 32 bit addressing 1: 64 bit addressing reset to 1 15:4 upstream memory base address r/w controls upstream memory base address. reset to 00000000h 14.1.32 upstream (s1 or s2 to p) memory limit register ? offset 50h bit function type description 19:16 64 bit addressing r/o 0: 32 bit addressing 1: 64 bit addressing reset to 1 31:20 upstream memory limit address r/w controls upstream memory limit address. reset to 000fffffh 14.1.33 upstream (s1 or s2 to p) memory base upper 32-bits register ? offset 54h bit function type description 31:0 upstream memory base address r/w defines bits [63:32] of the upstream memory base reset to 0
PI7C7300D 3-port pci-to-pci bridge page 88 of 107 pericom semiconductor november 2005 - revision 1.01 14.1.34 upstream (s1 or s2 to p) memory limit upper 32 bits register ? offset 58h bit function type description 31:0 upstream memory limit address r/w defines bits [63:32] of the upstream memory limit reset to 0 14.1.35 p_serr# event disable register ? offset 64h bit function type description 0 reserved r/o reserved. retu rns 0 when read. reset to 0 1 posted write parity error r/w controls PI7C7300D?s ability to asse rt p_serr# when it is unable to transfer any read data from the target after 2 24 attempts. 0: p_serr# is asserted if this ev ent occurs and the serr# enable bit in the command register is set. 1: p_serr# is not assert if this ev ent occurs. reset to 0 2 posted write non-delivery r/w controls PI7C7300D?s ability to asse rt p_serr# when it is unable to transfer delayed write data after 2 24 attempts. 0: p_serr# is asserted if this ev ent occurs and the serr# enable bit in the command register is set 1: p_serr# is not asserted if this event occurs reset to 0 3 target abort during posted write r/w controls PI7C7300D?s ability to a ssert p_serr# when it receives a target abort when attempting to deliver posted write data. 0: p_serr# is asserted if this ev ent occurs and the serr# enable bit in the command register is set 1: p_serr# is not asserted if this event occurs reset to 0 4 master abort on posted write r/w controls PI7C7300D?s ability to a ssert p_serr# when it receives a master abort when attempting to deliver posted write data. 0: p_serr# is asserted if this ev ent occurs and the serr# enable bit in the command register is set 1: p_serr# is not asserted if this event occurs reset to 0 5 delayed write non-delivery r/w controls PI7C7300D?s ability to asse rt p_serr# when it is unable to transfer delayed write data after 2 24 attempts. 0: p_serr# is asserted if this ev ent occurs and the serr# enable bit in the command register is set 1: p_serr# is not asserted if this event occurs reset to 0
PI7C7300D 3-port pci-to-pci bridge page 89 of 107 pericom semiconductor november 2005 - revision 1.01 bit function type description 6 delayed read ? no data from target r/w controls PI7C7300D?s ability to asse rt p_serr# when it is unable to transfer any read data from the target after 2 24 attempts. 0: p_serr# is asserted if this ev ent occurs and the serr# enable bit in the command register is set 1: p_serr# is not asserted if this event occurs reset to 0 7 reserved r/o reserved. retu rns 0 when read. reset to 0 14.1.36 secondary clock control register ? offset 68h configuration register 1 bit function type description 1:0 clock 0 disable r/w if either bit is 0, then s1_clkout [0] is enabled. if both bits are 1, the s1_clkout [0] is disabled. 3:2 clock 1 disable r/w if either bit is 0, then s1_clkout [1] is enabled. if both bits are 1, the s1_clkout [1] is disabled. 5:4 clock 2 disable r/w if either bit is 0, then s1_clkout [2] is enabled. if both bits are 1, the s1_clkout [2] is disabled. 7:6 clock 3 disable r/w if either bit is 0, then s1_clkout [3] is enabled. if both bits are 1, the s1_clkout [3] is disabled. 9:8 clock 4 disable r/w if either bit is 0, then s1_clkout [4] is enabled. if both bits are 1, the s1_clkout [4] is disabled. 11:10 clock 5 disable r/w if either bit is 0, then s1_clkout [5] is enabled. if both bits are 1, the s1_clkout [5] is disabled. 13:12 clock 6 disable r/w if either bit is 0, then s1_clkout [6] is enabled. if both bits are 1, the s1_clkout [6] is disabled. 15:14 clock 7 disable r/w if either bit is 0, then s1_clkout [7] is enabled. if both bits are 1, the s1_clkout [7] is disabled. configuration register 2 bit function type description 1:0 clock 0 disable r/w if either bit is 0, then s2_clkout [0] is enabled. if both bits are 1, the s2_clkout [0] is disabled. 3:2 clock 1 disable r/w if either bit is 0, then s2_clkout [1] is enabled. if both bits are 1, the s2_clkout [1] is disabled. 5:4 clock 2 disable r/w if either bit is 0, then s2_clkout [2] is enabled. if both bits are 1, the s2_clkout [2] is disabled. 7:6 clock 3 disable r/w if either bit is 0, then s2_clkout [3] is enabled. if both bits are 1, the s2_clkout [3] is disabled. 9:8 clock 4 disable r/w if either bit is 0, then s2_clkout [4] is enabled. if both bits are 1, the s2_clkout [4] is disabled. 11:10 clock 5 disable r/w if either bit is 0, then s2_clkout [5] is enabled. if both bits are 1, the s2_clkout [5] is disabled. 13:12 clock 6 disable r/w if either bit is 0, then s2_clkout [6] is enabled. if both bits are 1, the s2_clkout [6] is disabled. 15:14 clock 7 disable r/w if either bit is 0, then s2_clkout [7] is enabled. if both bits are 1, the s2_clkout [7] is disabled. 14.1.37 port option register ? offset 74h bit function type description 0 reserved r/o reserved. return s 0 when read. reset to 0.
PI7C7300D 3-port pci-to-pci bridge page 90 of 107 pericom semiconductor november 2005 - revision 1.01 bit function type description 1 primary memr command alias enable r/w controls PI7C7300D?s detection mechanism for matching memory read retry cycles from the initiator on the primary interface 0: exact matching for non-posted memory write retry cycles from initiator on the primary interface 1: alias memrl or memrm to memr for memory read retry cycles from the initiator on the primary interface reset to 0 2 primary memw command alias enable r/w controls PI7C7300D?s detection mechanism for matching non-posted memory write retry cycles from th e initiator on the primary interface 0: exact matching for non-posted memory write retry cycles from initiator on the primary interface 1: alias memwi to memw for non-posted memory write retry cycles from initiator on the primary interface reset to 0 3 secondary memr command alias enable r/w controls PI7C7300D?s detection mechanism for matching memory read retry cycles from the initiator on s1 0: exact matching for memory read retry cycles from initiator on the s1 or s2 interface 1: alias memrl or memrm to memr for memory read retry cycles from initiator on the s1 or s2 interface reset to 0 4 secondary memw command alias enable r/w controls PI7C7300D?s detection mechanism for matching non-posted memory write retry cycles from th e initiator on the primary interface 0: exact matching for non-posted memory write retry cycles from initiator on the s1 or s2 interface 1: alias memwi to memw for non-posted memory write retry cycles from initiator on the s1 or s2 interface reset to 0 8:5 reserved r/o reserved. retu rns 0 when read. reset to 0. 9 enable long request r/w controls PI7C7300D?s ability to enable long requests for lock cycles 0: normal lock operation 1: enable long request for lock cycle reset to 0 10 enable secondary to hold request longer r/w control?s PI7C7300D?s ability to enable s1 or s2 to hold requests longer. 0: internal s1 or s2 master will release req# after frame# assertion 1: internal s1 or s2 master will hold req# until there is no transactions pending in fifo or until terminated by target reset to 0 11 enable primary to hold request longer r/w control?s PI7C7300D?s ability to hol d requests longer at the primary port. 0: internal primary master w ill release req# after frame# assertion 1: internal primary master will hold req# until there is no transactions pending in fifo or until terminated by target reset to 0 15:12 reserved r/o reserved. retu rns 0 when read. reset to 0.
PI7C7300D 3-port pci-to-pci bridge page 91 of 107 pericom semiconductor november 2005 - revision 1.01 14.1.38 master timeout counter register ? offset 74h bit function type description 31:16 master timeout r/w holds the maximum number of pci clocks that PI7C7300D will wait for initiator to retry the same cycl e before reporting timeout. master timeout occurs after 2 10 pci clocks. default is 400h. 14.1.39 retry counter register ? offset 78h bit function type description 31:0 retry counter r/w holds the maximum number of attempts that PI7C7300D will try before reporting retry timeout. retry count set at 2 24 pci clocks. default is 0100 0000h. 14.1.40 sampling timer register ? offset 7ch bit function type description 31:0 sampling timer r/w sets the duration (in pci cloc ks) during which PI7C7300D will record the number of successful transactions for performance evaluation. the recording will start right after this register is programmed and will be cleared afte r the timer expires. maximum period is 128 seconds at 33mhz. reset to 0. 14.1.41 secondary successful i/o read counter register ? offset 80h bit function type description 31:0 successful i/o read counts on s1 or s2 r/w stores the successful i/o read count on s1 or s2 and is updated when the sampling timer is active. reset to 0 14.1.42 secondary successful i/o write counter register ? offset 84h bit function type description 31:0 successful i/o write counts on s1 or s2 r/w stores the successful i/o write count on s1 or s2 and is updated when the sampling timer is active. reset to 0
PI7C7300D 3-port pci-to-pci bridge page 92 of 107 pericom semiconductor november 2005 - revision 1.01 14.1.43 secondary successful memory read counter register ? offset 88h bit function type description 31:0 successful memory read counts on s1 or s2 r/w stores the successful memory read count on s1 or s2 and is updated when the sampling timer is active. reset to 0 14.1.44 secondary successful memory write counter register ? offset 8ch bit function type description 31:0 successful memory write counts on s1 or s2 r/w stores the successful memory write count on s1 or s2 and is updated when the sampling timer is active. reset to 0 14.1.45 primary successful i/o read counter register ? offset 90h bit function type description 31:0 successful i/o read counts on primary r/w stores the successful i/o read count on primary and is updated when the sampling timer is active. reset to 0 14.1.46 primary successful i/o write counter register ? offset 94h bit function type description 31:0 successful i/o write counts on primary r/w stores the successful i/o write count on primary and is updated when the sampling timer is active. reset to 0 14.1.47 primary successful memory read counter register ? offset 98h bit function type description 31:0 successful memory read counts on primary r/w stores the successful memory read count on primary and is updated when the sampling timer is active. reset to 0
PI7C7300D 3-port pci-to-pci bridge page 93 of 107 pericom semiconductor november 2005 - revision 1.01 14.1.48 primary successful memory write counter register ? offset 9ch bit function type description 31:0 successful memory write counts on primary r/w stores the successful memory write count on primary and is updated when the sampling timer is active. reset to 0 14.1.49 capability id register ? offset b0h bit function type description 7:0 capability id r/o capability id for slot identification 00h: reserved 01h: pci power management (pcipm) 02h: accelerated graphics port (agp) 03h: vital product data (vpd) 04h: slot identification (si) 05h: message signaled interrupts (msi) 06h: compact pci hot swap (chs) 07h ? 255h: reserved reset to 04h 14.1.50 next pointer register ? offset b0h bit function type description 15:8 next pointer r/o reset to 1100 0000: next pointer (c0h if hs_en is 1) 0000 0000: next pointer (00h if hs_en is 0) 14.1.51 slot number register ? offset b0h bit function type description 20:16 expansion slot number r/w determines expansion slot number reset to 0 21 first in chassis r/w first in chassis reset to 0 23:22 reserved r/o reserved. retu rns 0 when read. reset to 0. 14.1.52 chassis number register ? offset b0h bit function type description 31:24 chassis number register r/w chassis number register. reset to 0
PI7C7300D 3-port pci-to-pci bridge page 94 of 107 pericom semiconductor november 2005 - revision 1.01 14.1.53 capability id register ? offset c0h bit function type description 7:0 capability id for hot swap r/o capability id for hot swap 00h: reserved 01h: pci power management (pcipm) 02h: accelerated graphics port (agp) 03h: vital product data (vpd) 04h: slot identification (si) 05h: message signaled interrupts (msi) 06h: compact pci hot swap (chs) 07h ? 255h: reserved reset to 06h 14.1.54 next pointer register ? offset c0h bit function type description 15:8 next pointer r/o 00: end of pointer (00h). 14.1.55 hot swap control and status register ? offset c0h bit function type description 16 not available r/o not used. re turns 0 when read. reset to 0 17 enum signal mask r/w 0: mask enum# signal 1: enable enum# signal 18 not available r/o not used. re turns 0 when read. reset to 0 19 led on/off r/w loo signal (led on/off) 0: led on 1: led off reset to 0 21:20 not available r/o not used. re turns 0 when read. reset to 0 22 enum# status ? extraction r/w 0: enum# asserted 1: enum# not asserted reset to 0 23 enum# status ? insertion r/w 0: enum# asserted 1: enum# not asserted reset to 0 31:24 reserved r/o reserved. retu rns 0 when read. reset to 0 15 bridge behavior a pci cycle is initiated by asserting the frame# signal. in a bridge, there are a number of possibilities. those possibilities are summarized in the table below:
PI7C7300D 3-port pci-to-pci bridge page 95 of 107 pericom semiconductor november 2005 - revision 1.01 15.1 bridge actions for various cycle types initiator target response master on primary target on primary PI7C7300D does not respond. it detects this situation by decoding the address as well as monitoring the p_devsel# for other fast and medium devices on the primary port. master on primary target on secondary PI7C7300D asserts p_devsel#, terminates the cycle normally if it is able to be posted, otherwise return with a retry. it then passes the cycle to the appropriate port. when the cycle is complete on the target port, it will wait for the initiator to repeat the same cycle and end with normal termination. master on primary target not on primary nor secondary port PI7C7300D does not respond and the cycle will terminate as master abort. master on secondary target on the same secondary port PI7C7300D does not respond. master on secondary target on primary or the other secondary port PI7C7300D asserts s1_devsel# or s2_devsel#, terminates the cycle normally if it is able to be posted, otherwise returns with a retry. it then passes the cycle to th e appropriate port. when cycle is complete on the target port, it will wait for the initia tor to repeat the same cycle and end with normal termination. master on secondary target not on primary nor the other secondary port PI7C7300D does not respond. 15.2 transaction ordering to maintain data coherency and consiste ncy, PI7C7300D complies with the ordering rules put forth in the pci local bus specification, rev 2.2 . the following table summarizes the ordering relationship of all the transactions through the bridge. pmw - posted write (either memory write or memory write & invalidate) drr - delayed read request (all memory read, i/o read & configuration read) dwr - delayed write request (i/o write & confi guration write, memory write to certain location) drc - delayed read completion (all memory read, i/o read & configuration read) dwc - delayed write completion (i/o write & configuration write, memory write to ccertain location cycle type shown on each row is the subseque nt cycle after the previous shown on the column. can row pass column? pmw column 1 drr column 2 dwr column 3 drc column 4 dwc column 5 pmw (row 1) no yes yes yes yes drr (row 2) no no no yes yes dwr (row 3) no no no yes yes drc (row 4) no yes yes no no
PI7C7300D 3-port pci-to-pci bridge page 96 of 107 pericom semiconductor november 2005 - revision 1.01 dwc (row 5) yes yes yes no no in row 1 column 1, pmw cannot pass the previous pmw and that means they must complete on the target bus in the order in which they were received in the initiator bus. in row 2 column1,drr cannot pass the previous pmw and that means the previous pmw heading to the same direction must be completed before the drr can be attempted on the target bus. in row 1 column 2, pmw can pass the prev ious drr as long as the drr reaches the head of the delayed transaction queue. 15.3 abnormal termination (initiated by bridge master) 15.3.1 master abort master abort indicates that when PI7C7300D acts as a ma ster and receives no response (i.e., no target asserts devsel# or s1_devsel# or s2_devsel#) from a target, the bridge deasserts frame# and then deasserts irdy#. 15.3.2 parity and error reporting parity must be checked for all addresses and write data. parity is defined on the p_par, s1_par, and s2_par signals. parity should be even (i. e. an even number of?1?s) across ad, cbe, and par. parity information on pa r is valid the cycle after ad and cbe are valid. for reads, even parity must be generated using the initiators cbe signals combined with the read data. again, the par signal corresponds to read data from the previous data phase cycle. 15.3.3 reporting parity errors for all address phases, if a parity error is detected, the error should be reported on the p_serr# signal by asserting p_serr# for one cycle and then 3-stating two cycles after the bad address. p_serr# can only be asserted if bit 6 and 8 in the command register are both set to 1. for write data phases, a pa rity error should be reported by asserting the p_perr# signal two cycles after the data phase and should remain asserted for one cycle when bit 6 in the command register is set to a 1. the target reports any type of data parity errors during write cycles, while the master reports data parity errors during read cycles. detection of an address parity error will cause the pci-to-pci bridge target to not claim the bus (p_devsel# remains inactive) and the cycle will then terminate with a master abort. when the bridge is acting as master, a data parity error during a read cycle results in the bridge master initiating a master abort.
PI7C7300D 3-port pci-to-pci bridge page 97 of 107 pericom semiconductor november 2005 - revision 1.01 15.3.4 secondary idsel mapping when PI7C7300D detects a type 1 configuration transaction for a device connected to the secondary, it translates the type 1 transaction to type 0 transaction on the downstream interface. type 1 configuration form at uses a 5-bit field at p_ad[15:11] as a device number. this is translated to s1_ad[31:16] or s2_ad[31:16] by PI7C7300D. 16 ieee 1149.1 compatible jtag controller an ieee 1149.1 compatible test access port (tap) controller and a ssociated tap pins are provided to support boundary scan in PI7C7300D for board-level continuity test and diagnostics. the tap pins assigned are tck, tdi, tdo, tms and trst#. all digital input, output, input/output pins are tested except tap pins and clock pin. the ieee 1149.1 test logic consists of a tap controller, an instru ction register, and a group of test data registers including bypass, device identification and boundary scan registers. the tap controller is a synchronous 16-state machine driven by the test clock (tck) and the test mode select (tms) pins . an independent power on reset circuit is provided to ensure the machine is in test_logic_reset state at power-up. the jtag signal lines are not active when the pc i resource is operating pci bus cycles. PI7C7300D implements 3 basic instructions: bypass, sample/preload, and extest. 16.1 boundary scan architecture boundary-scan test logic consists of a boundary-scan register and support logic. these are accessed through a test access port (tap ). the tap provides a simple serial interface that allows all processor signal pins to be driven and/or sampled, thereby providing direct control and monitoring of processor pins at the system level. this mode of operation is valuable for design debugging and fault diagnosis since it permits examination of connections not nor mally accessible to the test system. the following subsections describe the boundary-scan test logic elements: tap pins, instruction register, test data registers and tap controller. error! reference source not found. illustrates how these pieces fit t ogether to form the jtag unit.
PI7C7300D 3-port pci-to-pci bridge figure 16-1 test access port block diagram 16.1.1 tap pins the PI7C7300D?s tap pins form a serial port composed of four input connections (tms, tck, trst# and tdi) and one output connection (tdo). these pins are described in table 16-1. the tap pins provide access to the instruction register and the test data registers. 16.1.2 instruction register the instruction register (ir) holds instruction codes. these codes are shifted in through the test data input (tdi) pin. the instruction codes are used to select the specific test operation to be performed and the test data register to be accessed. the instruction register is a parallel-loadable, master/slave-configured 4-bit wide, serial- shift register with latched outputs. data is shifted into and out of the ir serially through the tdi pin clocked by the rising edge of tck. the shifted-in instruction becomes active upon latching from the master stage to the slave stage. at that time the ir outputs along with the tap finite state mach ine outputs are decoded to select and control the test data register selected by that instruction. upon latching, all actions caused by any previous instructions terminate. the instruction determines the test to be perfo rmed, the test data register to be accessed, or both. the ir is two bits wide. when the ir is selected, the most significant bit is connected to tdi, and the least significant b it is connected to tdo. the value presented on the tdi pin is shifted into the ir on each rising edge of tck. the tap controller captures fixed parallel data (1101 binary). wh en a new instruction is shifted in through tdi, the value 1101(binary) is always shifted out through tdo, least significant bit first. this helps identify instructions in a long chain of serial data from several devices. page 98 of 107 pericom semiconductor november 2005 - revision 1.01
PI7C7300D 3-port pci-to-pci bridge page 99 of 107 pericom semiconductor november 2005 - revision 1.01 upon activation of the trst# reset pin, the latched instruction asynchronously changes to the id code instruction. when the tap controller moves into the test state other than by reset activation, the opcode changes as tdi shifts, and becomes active on the falling edge of tck. 16.2 boundary-scan instruction set the PI7C7300D supports three mandatory boundary-scan instructions (bypass, sample/preload and extest). the table shown below lists the PI7C7300D?s boundary-scan instruction codes. the ?reserve d? code should not be used. instruction code (binary) instruction name instruction code (binary) instruction name 0000 extest 0101 reserved 0001 sample/preload 1111 bypass table 16-1 tap pins instruction / requisite opcode (binary) description extest ieee 1149.1 required 0000 extest initiates testing of external circuitry, typically board-level interconnects and off chip circ uitry. extest connects the boundary-scan register between tdi and tdo. when extest is selected, all output signal pin values are driven by values shifted into the boundary-scan register and may change only of the falling edge of tck. also, when extest is selected, all system input pin states must be loaded into the boundary-scan register on the rising-edge of tck. sample/preload ieee 1149.1 required 0001 sample/preload performs two functions: 1. a snapshot of the sample instruction is captured on the rising edge of tck without interfering with normal operation. the instruction causes boundary-scan register cells associated with outputs to sample the value being driven. 2. on the falling edge of tck, the data held in the boundary-scan cells is transferred to the slav e register cells. typically, the slave latched data is applied to the system outputs via the extest instruction. idcode ieee 1149.1 required 0101 reserved bypass ieee 1149.1 required 1111 bypass instruction selects the one-bit bypass register between tdi and tdo pins. 0 (binary) is the only instruction that accesses the bypass register. while this instruction is in effect, all other test data registers have no effect on system operation. test data registers with both test and system functionality perform their system functions when this instruction is selected. 16.3 tap test data registers the PI7C7300D contains two test data registers (bypass and boundary-scan). each test data register selected by th e tap controller is connected se rially between tdi and tdo. tdi is connected to the test data register?s most significant bit. tdo is connected to the least significant bit. data is shifted one bit position within the register towards tdo on
PI7C7300D 3-port pci-to-pci bridge page 100 of 107 pericom semiconductor november 2005 - revision 1.01 each rising edge of tck. while any register is selected, data is transferred from tdi to tdo without inversion. the following sections describe each of the test data registers. 16.4 bypass register the required bypass register, a one-bit shift register, provides the shortest path between tdi and tdo when a bypass instruction is in effect. this allows rapid movement of test data to and from other components on the board. this path can be selected when no test operation is being performed on the PI7C7300D. 16.5 boundary-scan register the boundary-scan register contai ns a cell for each pin as well as control cells for i/o and the high-impedance pin. table 16-2 shows the bit order of the PI7C7300D boundary-scan register. all table cells that contain ?control? select the direction of bi-directional pins or high-impedance output pins. when a ?0? is loaded into the control cell, the associated pin(s) are high- impedance or selected as input. the boundary-scan register is a required set of serial-shiftable register cells, configured in master/slave stages and connected betw een each of the PI7C7300D?s pins and on-chip system logic. the vdd, gnd, pll, agnd, avdd and jtag pins are not in the boundary-scan chain. the boundary-scan register cells are dedicated logic and do not have any system function. data may be loaded into the boundary-scan register master cells from the device input pins and output pin-drivers in pa rallel by the mandatory sample/preload and extest instructions. parallel loading takes place on the rising edge of tck. data may be scanned into the boundary-scan register serially via the tdi serial input pin, clocked by the rising edge of tck. when the required data has been loaded into the master-cell stages, it can be driven into the system logic at input pins or onto the output pins on the falling edge of tck state. data may also be shifted out of the boundary-scan register by means of the tdo serial output pin at the falling edge of tck. 16.6 tap controller the tap (test access port) controller is a 4-state synchronous finite state machine that controls the sequence of test logic operations. the tap can be controlled via a bus master. the bus master can be either automatic test equipment or a component (i.e., pld) that interfaces to the tap. the tap controller changes state only in response to a rising edge of tck. the value of the test mode state (tms) input signal at a rising edge of tck controls the sequence of state changes. the tap controller is initialized after power-up by applying a low to the trst# pin. in addition, the tap controller can be initialized by applying a high signal level on the tms input for a minimum of five tck periods.
PI7C7300D 3-port pci-to-pci bridge page 101 of 107 pericom semiconductor november 2005 - revision 1.01 for greater detail on the behavior of the tap c ontroller, test logic in each controller state and the state machine and public instructi ons, refer to the ieee 1149.1 standard test access port and boundary-scan architect ure document (available from the ieee). table 16-2 jtag boundary register order order pin names type order pin names type 0 enum# output 60 p_stop# control 1 enum# control 61 p_perr# bidir 2 hs_en input 62 p_perr# control 3 s_cfn# input 63 p_lock# input 4 s1_en input 64 p_serr# output 5 s2_en input 65 p_serr# control 6 scan_tm# input 66 p_ad[13] bidir 7 scan_en input 67 p_ad[13] control 8 pll_tm input 68 p_ad[14] bidir 9 by_pass input 69 p_ad[14] control 10 s2_m66en input 70 p_ad[11] bidir 11 p_reset# input 71 p_ad[11] control 12 p_gnt# input 72 p_ad[15] bidir 13 p_req# output 73 p_ad[15] control 14 p_req# control 74 p_ad[12] bidir 15 p_ad[30] bidir 75 p_ad[12] control 16 p_ad[30] control 76 p_ad[8] bidir 17 p_ad[31] bidir 77 p_ad[8] control 18 p_ad[31] control 78 p_cbe[1] bidir 19 p_ad[27] bidir 79 p_cbe[1] control 20 p_ad[27] control 80 p_ad[9] bidir 21 p_ad[26] bidir 81 p_ad[9] control 22 p_ad[26] control 82 p_ad[5] bidir 23 p_ad[28] bidir 83 p_ad[5] control 24 p_ad[28] control 84 p_m66en input 25 p_ad[29] bidir 85 p_ad[6] bidir 26 p_ad[29] control 86 p_ad[6] control 27 p_cbe[3] bidir 87 p_ad[2] bidir 28 p_cbe[3] control 88 p_ad[2] control 29 p_ad[24] bidir 89 p_par bidir 30 p_ad[24] control 90 p_par control 31 p_ad[25] bidir 91 p_ad[0] bidir 32 p_ad[25] control 92 p_ad[0] control 33 p_ad[23] bidir 93 p_cbe[0] bidir 34 p_ad[23] control 94 p_cbe[0] control 35 p_ad[22] bidir 95 p_ad[7] bidir 36 p_ad[22] control 96 p_ad[7] control 37 p_idsel input 97 p_ad[10] bidir 38 p_ad[21] bidir 98 p_ad[10] control 39 p_ad[21] control 99 p_ad[1] bidir 40 p_ad[20] bidir 100 p_ad[1] control 41 p_ad[20] control 101 p_ad[3] bidir 42 p_ad[19] bidir 102 p_ad[3] control 43 p_ad[19] control 103 p_ad[4] bidir 44 p_ad[18] bidir 104 p_ad[4] control 45 p_ad[18] control 105 s1_ad[0] bidir 46 p_ad[17] bidir 106 s1_ad[0] control 47 p_ad[17] control 107 s1_ad[1] bidir 48 p_ad[16] bidir 108 s1_ad[1] control 49 p_ad[16] control 109 s1_ad[2] bidir 50 p_cbe[2] bidir 110 s1_ad[2] control 51 p_cbe[2] control 111 s1_ad[5] bidir
PI7C7300D 3-port pci-to-pci bridge page 102 of 107 pericom semiconductor november 2005 - revision 1.01 order pin names type order pin names type 52 p_frame# bidir 112 s1_ad[5] control 53 p_frame# control 113 s1_ad[3] bidir 54 p_irdy# bidir 114 s1_ad[3] control 55 p_irdy# control 115 s1_ad[4] bidir 56 p_trdy# bidir 116 s1_ad[4] control 57 p_devsel#/p_trdy# control 117 s1_cbe[0] bidir 58 p_devsel# bidir 118 s1_cbe[0] control 59 p_stop# bidir 119 s1_ad[7] bidir 120 s1_ad[7] control 182 s1_ad[28] control 121 s1_ad[6] bidir 183 s1_ad[30] bidir 122 s1_ad[6] control 184 s1_ad[30] control 123 s1_ad[8] bidir 185 s1_ad[31] bidir 124 s1_ad[8] control 186 s1_ad[31] control 125 s1_ad[9] bidir 187 s1_ad[27] bidir 126 s1_ad[9] control 188 s1_ad[27] control 127 s1_ad[10] bidir 189 s1_ad[24] bidir 128 s1_ad[10] control 190 s1_ad[24] control 129 s1_ad[11] bidir 191 s1_ad[18] bidir 130 s1_ad[11] control 192 s1_ad[18] control 131 s1_ad[12] bidir 193 s1_gnt#[0] output 132 s1_ad[12] control 194 s1_gnt#[0] control 133 s1_ad[14] bidir 195 s1_req#[0] input 134 s1_ad[14] control 196 s1_req#[1] input 135 s1_ad[13] bidir 197 s1_gnt#[1] output 136 s1_ad[13] control 198 s1_gnt#[2] output 137 s1_ad[15] bidir 199 s1_req#[2] input 138 s1_ad[15] control 200 s1_req#[3] input 139 s1_serr# input 201 s1_gnt#[3] output 140 s1_par bidir 202 s1_gnt#[4] output 141 s1_par control 203 s1_req#[4] input 142 s1_cbe[1] bidir 204 s1_req#[5] input 143 s1_cbe[1] control 205 s1_gnt#[5] output 144 s1_devsel# bidir 206 s1_gnt#[6] output 145 s1_devsel#/s1_trdy# control 207 s1_req#[6] input 146 s1_stop# bidir 208 s1_req#[7] input 147 s1_stop# control 209 s1_gnt#[7] output 148 s1_lock# bidir 210 s1_reset# output 149 s1_lock# control 211 s2_ad[0] bidir 150 s1_perr# bidir 212 s2_ad[0] control 151 s1_perr# control 213 s2_ad[1] bidir 152 s1_frame# bidir 214 s2_ad[1] control 153 s1_frame# control 215 s2_ad[2] bidir 154 s1_irdy# bidir 216 s2_ad[2] control 155 s1_irdy# control 217 s2_ad[3] bidir 156 s1_trdy# bidir 218 s2_ad[3] control 157 s1_ad[17] bidir 219 s2_ad[4] bidir 158 s1_ad[17] control 220 s2_ad[4] control 159 s1_ad[16] bidir 221 s2_ad[5] bidir 160 s1_ad[16] control 222 s2_ad[5] control 161 s1_ad[20] bidir 223 s2_ad[6] bidir 162 s1_ad[20] control 224 s2_ad[6] control 163 s1_cbe[2] bidir 225 s2_ad[7] bidir 164 s1_cbe[2] control 226 s2_ad[7] control 165 s1_ad[19] bidir 227 s2_cbe[0] bidir 166 s1_ad[19] control 228 s2_cbe[0] control 167 s1_cbe[3] bidir 229 s2_ad[8] bidir 168 s1_cbe[3] control 230 s2_ad[8] control 169 s1_ad[23] bidir 231 s2_ad[10] bidir 170 s1_ad[23] control 232 s2_ad[10] control 171 s1_ad[26] bidir 233 s2_ad[9] bidir
PI7C7300D 3-port pci-to-pci bridge page 103 of 107 pericom semiconductor november 2005 - revision 1.01 order pin names type order pin names type 172 s1_ad[26] control 234 s2_ad[9] control 173 s1_ad[22] bidir 235 s2_ad[11] bidir 174 s1_ad[22] control 236 s2_ad[11] control 175 s1_ad[25] bidir 237 s1_m66en input 176 s1_ad[25] control 238 s2_ad[12] bidir 177 s1_ad[29] bidir 239 s2_ad[12] control 178 s1_ad[29] control 240 s2_ad[14] bidir 179 s1_ad[21] bidir 241 s2_ad[14] control 180 s1_ad[21] control 242 s2_cbe[1] bidir 181 s1_ad[28] bidir 243 s2_cbe[1] control 244 s2_ad[15] bidir 282 s2_ad[23] bidir 245 s2_ad[15] control 283 s2_ad[23] control 246 s2_par bidir 284 s2_cbe[3] bidir 247 s2_par control 285 s2_cbe[3] control 248 s2_serr# input 286 s2_ad[25] bidir 249 s2_lock# bidir 287 s2_ad[25] control 250 s2_lock# control 288 s2_ad[26] bidir 251 s2_trdy# bidir 289 s2_ad[26] control 252 s2_devsel#/s2_trdy# control 290 s2_ad[28] bidir 253 s2_stop# bidir 291 s2_ad[28] control 254 s2_stop# control 292 s2_ad[27] bidir 255 s2_irdy# bidir 293 s2_ad[27] control 256 s2_irdy# control 294 s2_ad[29] bidir 257 s2_cbe[2] bidir 295 s2_ad[29] control 258 s2_cbe[2] control 296 s2_ad[30] bidir 259 s2_ad[13] bidir 297 s2_ad[30] control 260 s2_ad[13] control 298 s2_ad[31] bidir 261 s2_ad[21] bidir 299 s2_ad[31] control 262 s2_ad[21] control 300 s2_gnt#[0] output 263 s2_perr# bidir 301 s2_gnt#[0] control 264 s2_perr# control 302 s2_req#[0] input 265 s2_ad[16] bidir 303 s2_req#[1] input 266 s2_ad[16] control 304 s2_gnt#[1] output 267 s2_frame# bidir 305 s2_gnt#[2] output 268 s2_frame# control 306 s2_req#[2] input 269 s2_devsel# bidir 307 s2_req#[3] input 270 s2_ad[19] bidir 308 s2_gnt#[3] output 271 s2_ad[19] control 309 s2_gnt#[4] output order pin names type order pin names type 272 s2_ad[17] bidir 310 s2_req#[4] input 273 s2_ad[17] control 311 s2_req#[5] input 274 s2_ad[18] bidir 312 s2_gnt#[5] output 275 s2_ad[18] control 313 s2_gnt#[6] output 276 s2_ad[20] bidir 314 s2_req#[6] input 277 s2_ad[20] control 278 s2_ad[22] bidir 279 s2_ad[22] control 280 s2_ad[24] bidir 281 s2_ad[24] control 17 electrical and timing specifications 17.1 maximum ratings (above which the useful life may be impaired. for user guidelines, not tested).
PI7C7300D 3-port pci-to-pci bridge page 104 of 107 pericom semiconductor november 2005 - revision 1.01 storage temperature -65 c to 150 c ambient temperature with power applied -40 c to 85 c supply voltage to ground potentials (inputs and av cc , v dd only] -0.3v to 3.6v dc input voltage -0.5v to 3.6v note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rati ng only and functional operation of the device at these or any conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. 17.2 3.3v dc specifications symbol parameter condition min. max. units notes v dd , av cc supply voltage 3 3.6 v v ih input high voltage 0.5 v dd v dd + 0.5 v 3 v il input low voltage -0.5 0.3 v dd v 3 v ih cmos input high voltage 0.7 v dd v dd + 0.5 v 1 v il cmos input low voltage -0.5 0.3 v dd v 1 v ipu input pull-up voltage 0.7 v dd v 3 i il input leakage current 0 < v in < v dd 10 a 3 v oh output high voltage i out = -500 a 0.9v dd v 3 v ol output low voltage i out = 1500 a 0.1 v dd v 3 v oh cmos output high voltage i out = -500 a v dd ? 0.5 v 2 v ol cmos output low voltage i out = 1500 a 0.5 v 2 c in input pin capacitance 10 pf 3 c clk clk pin capacitance 5 12 pf 3 c idsel idsel pin capacitance 8 pf 3 l pin pin inductance 20 nh 3 notes: 1. cmos input pins: s_cfn#, tck, tms, tdi, trst#, scan_en, scan_tm# 2. cmos output pin: tdo 3. pci pins: p_ad[31:0], p_cbe[3:0], p_par, p_frame#, p_irdy#, p_trdy#, p_devsel#, p_stop#, p_lock#, pidsel#, p_perr#, p_serr#, p_req#, p_gnt#, p_reset#, s1_ad[31:0], s2_ad[31:0], s1_cbe[3:0], s2_cbe[3:0], s1_par, s2_par, s1_frame#, s2_frame#, s1_irdy# , s2_irdy#, s1_trdy#, s2_trdy#, s1_devsel#, s2_devsel#, s1_stop# , s2_stop#, s1_lock#, s2_lock#, s1_perr#, s2_perr#, s1_s err#, s2_serr#, s1_req [7:0]#, s2_req[6:0]#, s1_gnt[7:0]#, s2_gnt[6:0], s1_reset# , s2_reset#, s1_en, s2_en, hsled, hs_sw#, hs_en, enum#.
PI7C7300D 3-port pci-to-pci bridge 17.3 3.3v ac specifications figure 17-1 pci signal ti ming measurement conditions 66 mhz 33 mhz symbol parameter min. max. min. max. units tsu input setup time to clk ? bused signals 1,2,3 3 - 7 - tsu(ptp) input setup time to clk ? point-to-point 1,2,3 5 - 10, 12 4 - th input signal hold time from clk 1,2 0 - 0 - tval clk to signal valid delay ? bused signals 1,2,3 2 6 2 11 tval(ptp) clk to signal valid delay ? point-to-point 1,2,3 2 6 2 12 ton float to active delay 1,2 2 - 2 - ns active to float delay 1,2 toff - 14 - 28 1. see figure 17-1 pci signal timing measurement conditions. 2. all primary interface signals are synchr onized to p_clk. all secondary interface signals are synchronized to e ither s1_clkout or s2_clkout. 3. point-to-point signals are p_req#, s1_req#[7:0], s2_req#[6:0], p_gnt#, s1_gnt#[7:0], s2_gnt#[6:0], hsled, hs_sw#, hs_en, and enum#. bused signals are p_ad, p_bde#, p_par, p_perr#, p_serr#, p_frame#, p_irdy#, p_trdy#, p_lock#, p_devsel#, p_stop#, p_idsel, s1_ad, s1_cbe#, s1_par, s1_perr#, s1_serr#, s1_frame#, s1_irdy#, s1_trdy#, s1_lock#, s1_devsel#, s1_stop#, s2_ad, s2_cbe#, s2_par, s2_perr#, s2_serr#, s2_frame#, s2_irdy#, s2_trdy#, s2_lock#, s2_devsel#, and s2_stop#. 4. req# signals have a setup of 10 and gnt# signals have a setup of 12. page 105 of 107 pericom semiconductor november 2005 - revision 1.01
PI7C7300D 3-port pci-to-pci bridge page 106 of 107 pericom semiconductor november 2005 - revision 1.01 17.4 primary and secondary buses at 66mhz clock timing symbol parameter condition min. max. units t skew skew among s1_clkout[7:0] 0 250 t skew skew among s2_clkout[6:0] 0 250 ps t delay delay between pclk and s1_c lkout[7:0] 20pf load 3.3 4.9 t delay delay between pclk and s2_c lkout[6:0] 20pf load 3.3 4.9 t cycle pclk, s1_clkout[7:0] cycle time 15 30 t cycle pclk, s2_clkout[6:0] cycle time 15 30 t high pclk, s1_clkout[7:0] high time 6 t high pclk, s2_clkout[6:0] high time 6 t low pclk, s1_clkout[7:0] low time 6 t low pclk, s_clkout[6:0] low time 6 ns 17.5 primary and secondary buses at 33mhz clock timing symbol parameter condition min. max. units t skew skew among s1_clkout[7:0] 0 250 t skew skew among s2_clkout[6:0] 0 250 ps t delay delay between pclk and s1_c lkout[7:0] 20pf load 3.3 4.9 t delay delay between pclk and s2_c lkout[6:0] 20pf load 3.3 4.9 t cycle pclk, s1_clkout[7:0] cycle time 30 t cycle pclk, s2_clkout[6:0] cycle time 30 t high pclk, s1_clkout[7:0] high time 11 t high pclk, s2_clkout[6:0] high time 11 t low pclk, s1_clkout[7:0] low time 11 t low pclk, s2_clkout[6:0] low time 11 ns 17.6 power consumption parameter typical units power consumption 2178 mw supply current, i cc 660 ma note: typical values are at vcc = 3.3v, ta = 25c, and all three ports running at 66mhz.
PI7C7300D 3-port pci-to-pci bridge 18 272-pin pbga package figure figure 18-1 272-pin pbga package top bottom thermal characteristics can be found on the web: http://www.pericom.com/packaging/mechanicals.php 18.1 part number ordering information part number pin ? package temperature PI7C7300Dna 272 ? pbga -40 c to 85 c PI7C7300Dnae 272 ? pbga, pb-free & green -40 c to 85 c page 107 of 107 pericom semiconductor november 2005 - revision 1.01

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